Data Sheet
37
Rev. 1.00
2017-07-31
TLE9263BQXV33
System Features
A wake event due to cyclic sense will set the respective bit WK1_WU, WK2_WU, or WK3_WU.
During Cyclic Sense,
WK_LVL_STAT
is updated only with the sampled voltage levels of the WKx pins in SBC
Normal or SBC Stop Mode.
The functionality of the sampling and different scenarios are depicted in
Figure 7
to
Figure 9
. The behavior in
SBC Stop and SBC Sleep Mode is identical except that in Stop Mode INT will be triggered to signal a change of
WK input levels and in SBC Sleep Mode, VCC1 will power-up instead.
Figure 7
Wake Input Timing
Figure 8
Cyclic Sense Example in SBC Stop Mode, HSx starts “OFF”/LOW, GND based WKx input
Filter time
t
FWK1
On Time
Periode
HS switch
t
Filter time
t
FWK1
HS on
Cyclic Sense
1st sample taken
as reference
Wake detection possible
on 2nd sample
High
n-1
Low
open
closed
Filter time
INT &
WK Bit Set
Learning
Cycle
WK
n-1
= High
WK
n
= Low
WK
n
≠
WK
n-1
wake event
WK
n+1
= Low
WK
n
= WK
n+1
no wake
WK
n+2
= High
WK
n+2
≠
WK
n+1
wake event
n
n+1
n+2
HS
WK
High
Low
Switch
INT
High
Low
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