Infineon TLE9263BQXV33 Manual Download Page 151 | Manualshive

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Data Sheet

151

Rev. 1.00

2017-07-31

TLE9263BQXV33

Serial Peripheral Interface

16.6

SPI Status Information Registers

READ/CLEAR Operation (see also

Chapter 16.3

):

• One 16-bit SPI command consist of two bytes:

- the 7-bit address and one additional bit for the register access mode and
- following the data byte
The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to
the SPI bits 8...15 (see also figure).

• There are two different bit types:

- ‘r’ = READ: read only bits (or reserved bits)
- ‘rc’ = READ/CLEAR: readable and clearable bits

• Reading a register is done byte wise by setting the SPI bit 7 to “0” (= Read Only)
• Clearing a register is done byte wise by setting the SPI bit 7 to “1”
• SPI status registers are in general not cleared or changed automatically (an exception are the

WD_FAIL

bits). This must be done by the microcontroller via SPI command

The registers are addressed wordwise.

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Summary of Contents for TLE9263BQXV33

Page 1: ...J2284 2 LIN transceivers LIN2 2A J2602 4 high side outputs 7 typ 2 HV GPIOs 3 HV wake inputs Integrated fail safe and supervision functions e g fail safe watchdog interrupt and reset outputs 16 bit S...

Page 2: ...t Mode 30 5 1 6 SBC Fail Safe Mode 31 5 1 7 SBC Development Mode 32 5 2 Wake Features 34 5 2 1 Cyclic Sense 34 5 2 1 1 Configuration and Operation of Cyclic Sense 35 5 2 1 2 Cyclic Sense in Low Power...

Page 3: ...ure 72 10 2 6 Bus Dominant Clamping 72 10 2 7 Undervoltage Detection 72 10 3 Electrical Characteristics 73 11 LIN Transceiver 80 11 1 Block Description 80 11 1 1 LIN Specifications 80 11 2 Functional...

Page 4: ...rning 115 15 6 1 VCC1 Undervoltage and Undervoltage Prewarning 115 15 6 2 VCC1 Overvoltage 116 15 7 VCC1 Short Circuit and VCC3 Diagnostics 117 15 8 VCC2 Undervoltage and VCAN Undervoltage 117 15 9 Th...

Page 5: ...Data Sheet 5 Rev 1 00 2017 07 31 TLE9263BQXV33 19 Revision History 175 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 6: ...provides the main functions such as a 3 3V low dropout voltage regulator LDO for e g a microcontroller supply another 5V low dropout voltage regulator with off board protection for e g sensor supply a...

Page 7: ...uirements for LIN CAN and FlexRay Interfaces in Automotive Applications Revision 1 3 2012 05 04 Four High Side Outputs 7 typ Dedicated supply pin for High Side Outputs TwoGeneralPurposeHigh VoltageIn...

Page 8: ...NT GND WAKE REGISTER VS VS Fail Safe RO FO3 TEST LIN cell TXDLIN 2 RXDLIN2 LIN2 FO2 FO1 VCC2 VCC2 High Side HS2 HS3 HS4 HS1 WK WK2 WK WK3 VCC3 VCC3REF VCC3SH VCC3B VSHS VS VSHS Alternative function fo...

Page 9: ...2 44 GND 43 LIN1 42 n c 41 CANH 40 CANL 39 GND 38 VCAN 37 13 VSHS 14 VS 15 VS 16 n c 17 VCC1 18 VCC2 19 n c 20 GND 21 FO1 22 WK1 23 WK2 24 WK3 25 TXDLIN2 26 RXDLIN2 27 CLK 28 SDI 29 SDO 30 CSN 31 INT...

Page 10: ...nalsupplyandvoltageregulators ConnectedtoBatteryVoltagewithexternalreverseprotectionDiodeandFilter against EMC 15 VS SupplyVoltage Supplyvoltageforchipinternalsupplyandvoltageregulators ConnectedtoBat...

Page 11: ...ernally not bonded 46 n c not connected internally not bonded 47 FO2 Fail Output 2 Side Indicator Side indicators 1 25Hz 50 duty cycle output Open drain Active LOW Alternative Function GPIO1 configura...

Page 12: ...ctable via SPI it must be ensured that the correct configurations are also selected via SPI in case it is not done automatically Please consult the respective chapter In addition following topics shal...

Page 13: ...1 25 Voltage Regulator 3 VCC3SH VCC3SH max VS 0 30 VS 0 30 V P_4 1 26 Wake Inputs WK1 3 VWK max 0 3 40 V P_4 1 6 Fail Pin FO1 VFO1 max 0 3 40 V P_4 1 7 Fail Pins FO2 FO3 TEST VFO2_3 max 0 3 VS 0 3 V...

Page 14: ...25 36 37 48 corner pins to GND VESD 22 750 750 V CDM5 P_4 1 21 1 Not subject to production test specified by design 2 Applies only if WK1 and WK2 are configured as alternative HV measurement function...

Page 15: ...e to out of spec operation VPOR f VS 5 5V Device will still be functional the specified electrical characteristics might not be ensured anymore The voltage regulators will enter the low drop operation...

Page 16: ...1 5W Board 76 2x114 3x1 5mm with 2 inner copper layers 35 m thick with thermal via array under the exposed pad contacting the first inner copper layer and 300mm2 cooling area on the bottom layer 70 m...

Page 17: ...tive peak threshold IStop_2 25 64 90 A 1 VCC2 3 HSx OFF CAN LINx WKx not wake capable Watchdog OFF no load on VCC1 I_PEAK_TH 1 P_4 4 35 Stop Mode current consumption high active peak threshold IStop_2...

Page 18: ...module Receive Only Mode ILIN RcvOnly 0 2 0 5 mA 2 SBC Normal Stop Mode LIN Receive Only Mode VTXDLIN VCC1 no RL on LIN P_4 4 12 Current consumption for WK1 3 wake capability all wake inputs IWake WKx...

Page 19: ...consumption for VCC3 in SBC Sleep Mode in stand alone configuration ISleep VCC3 25 40 60 A 1 3 SBC Sleep Mode VCC3 ON no load stand along config LIN CAN WK1 3 OFF P_4 4 21 Current consumption for VCC3...

Page 20: ...atures defined for SBC Sleep Mode also apply for SBC Stop Mode and vice versa unless otherwise specified 4 No pull up or pull down configuration selected 5 The specified WKx current consumption adder...

Page 21: ...either a wake event via CAN LINx or WKx occurs or the overtemperature condition is not present anymore A special mode called SBC Development Mode is available during software development or debugging...

Page 22: ...SBC Stop Mode VCC1 ON VCC2 fixed VCC3 fixed FOx fixed CAN fixed LINx fixed WD fixed HSx fixed SBC Restart Mode RO pin is asserted VCC1 ON ramping VCC2 OFF FOx 5 active fixed CAN 4 woken OFF WD OFF HSx...

Page 23: ...1 Figure 5 shows the timing diagram of the hardware configuration selection The hardware configuration is defined during SBC Init Mode The INT pin is internally pulled LOW with a weak pull down resist...

Page 24: ...tion can be identified by reading the SPI bit CFG in the HW_CTRL register and the CFGP bit in the WK_LVL_STAT register Table 5 shows the configurations and the device behavior in case of a watchdog tr...

Page 25: ...er 1st VCC1 OV SBC Fail Safe Mode 3 External pull up 0 1 1 x VCC1 OV 1 after 1st VCC1 OV SBC Restart Mode 4 No ext pull up 0 1 1 x VCC1 OV 1 after 1st VCC1 OV SBC Fail Safe Mode Downloaded from Arrow...

Page 26: ...nd to configure the watchdog see Chapter 15 2 Note At power up no VCC1_UV will be issued nor will FOx be triggered as long as VCC1 is below the VRT x threshold and if VS is below the VCC1 short circui...

Page 27: ...ed with HS1 4 and Timer1 or Timer 2 Cyclic wake can be configured with Timer1 or Timer2 Watchdog is configurable All FOx outputs are OFF by default Coming from SBC Restart Mode FOx can be active due t...

Page 28: ...gured in SBC Normal Mode Watchdog is fixed as configured in SBC Normal Mode SBC Soft Reset can be triggered FOx outputs are fixed i e the state from SBC Normal Mode is maintained An interrupt is trigg...

Page 29: ...e sources off in SBC Sleep Mode Doing so will set the SPI_FAIL flag and will bring the SBC into SBC Restart Mode In order to enter SBC Sleep Mode successfully all wake source signalization flags from...

Page 30: ...on previous SBC and transceiver mode see also Chapter 10 It is wake capable when it was in CAN Normal Receive Only or wake capable mode before SBC Restart Mode LIN is woken or OFF depending on previo...

Page 31: ...occurs To avoid any fast toggling behavior a filter time of typ 100ms tFS min is implemented Wake events during this time will be stored and will automatically lead to entering SBC Restart Mode after...

Page 32: ...longer than tTEST during the monitoring period then the SBC Development Mode is not reached The SBC will remain in this mode for all conditions and can only be left by powering down the device VS VPOR...

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Page 34: ...er the INT is pulled low SBC Normal Mode and Stop Mode or the SBC is woken enabling the VCC1 after SBC Sleep and SBC Fail Safe Mode Figure 5 Cyclic Sense Working Principle Switching Circuitry 1 4 High...

Page 35: ...ted HS switch in HS_CTRL_X Enable WKx as wake source with configured Timer in WK_FLT_CTRL Cyclic Sense starts ends by setting clearing On time Timer1 Timer2 Select Timer Period and desired On Time in...

Page 36: ...ween the current and previous cycle Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Download...

Page 37: ...gh WKn Low WKn WKn 1 wake event WKn 1 Low WKn WKn 1 no wake WKn 2 High WKn 2 WKn 1 wake event n n 1 n 2 HS WK High Low Switch INT High Low Downloaded from Arrow com Downloaded from Arrow com Downloade...

Page 38: ...will directly wake up from Sleep Mode by going via Restart Mode to Normal Mode a reset is issued The WKx_WU bit is seen as source for the wake This is implemented in order not to loose an wake event...

Page 39: ...Select Timer Period and any On Time in TIMERX_CTRL Periods 10 20 50 100 200ms 1s 2s On times any OFF LOW OFF HIGH are not allowed Disable Timer1 and or Timer2 as a wake source in WK_CTRL_1 To avoid u...

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Page 42: ...ed with lowest quiescent current consumption in SBC Stop Mode IStop_1 25 IStop_1 85 I_PEAK_TH 1 the higher VCC1 active peak threshold 2 is selected with an increased quiescent current consumption in S...

Page 43: ...alling VS 13 5V 40 C Tj 150 C I_PEAK_TH 0 P_6 3 17 VCC1 Active Peak Threshold 2 Transition threshold between low power and high power mode regulator IVCC1 Ipeak2 r 4 3 7 0 mA 2 ICC1 rising VS 13 5V 40...

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Page 47: ...ficient damping must be provided 7 2 1 Short to Battery Protection The output stage is protected for short to VBAT Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloa...

Page 48: ...VCC2 Active Peak Threshold Transition threshold between low power and high power mode regulator IVCC2 Ipeak r 1 9 3 5 mA 2 ICC2 rising VS 13 5V 40 C Tj 150 C P_7 3 15 VCC2 Active Peak Threshold Transi...

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Page 51: ...VS VCC3shunt Vshunt_threshold VREF State Machine ICC3base VCC3REF VCC3B VCC3SH VS Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded fr...

Page 52: ...l be automatically enabled again when exceeding this threshold voltage unless the control bit VCC3_VS_ UV_OFF is set i e in order to keep VCC3 enabled below VS_UV the bit VCC3_VS_ UV_OFF must be set V...

Page 53: ...on enabled and an undervoltage event is signaled with the bit VCC3_UV in the SUP_STAT_2 SPI register Note To avoid undesired current consumption increase of the device it must be ensured that VCC3 is...

Page 54: ...t limitation in this configuration and the shunt resistor is defining the load sharing ratio between the VCC1 and VCC3 load currents see Equation 8 2 in Chapter 8 4 Thus no overcurrent condition VCC3_...

Page 55: ...C3B VCC3SH VS RSHUNT T1 C2 C1 VS VCC13 Vcc3 Vcc1 ICC3 ICC1 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded...

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Page 57: ...g VS 13 5V 40 C Tj 150 C P_8 6 34 Parameters dependent on the Test Set up with external PNP device MJD 253 External Regulator Output Voltage VCC3 3 3V VCC3 out1 3 23 3 3 3 37 V 2 SBC Normal Mode load...

Page 58: ...one configuration 2 Tolerance includes load regulation and line regulation Table 14 Electrical Characteristics cont d Parameter Symbol Values Uni t Note or Test Condition Number Min Typ Max Downloaded...

Page 59: ...r better for loads up to 20mA and 2 with loads greater than 20mA In SBC Normal the 2 precision for 5V 3 3V tolerance is valid regardless of the applied load Downloaded from Arrow com Downloaded from A...

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Page 63: ...se feature The open load detection overcurrent shut down as well as overvoltage and undervoltage shutdown are available The overcurrent shutdown protection feature may influence the wake up behavior1...

Page 64: ...e the high side on time must be longer than tSD HS Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arr...

Page 65: ...ilter Time tOL HS 50 64 80 s 2 3 P_9 3 10 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Do...

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Page 67: ...SBC Init Mode is ON instead of OFF SBC Fail Safe Mode Wake Capable Example 11bit identifier 8Byte data Arbitration Phase 500kbps Data Phase 2Mbps average bit rate 1 14Mbps CAN Header Data phase Byte...

Page 68: ...AN OFF CAN EN t recessive TXD level required before start of transmission tCAN EN not ensured no transmission on bus CAN EN t Correct sequence Bus is enabled after tCAN EN tCAN EN not ensured no trans...

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Page 81: ...then it will remain OFF Behavior in SBC Development Mode LIN default value in SBC INIT MODE and entering SBC Normal Mode from SBC Init Mode is ON instead of OFF 1 after a wake event on LIN Bus SBC Fai...

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Page 83: ...n coming out of Sleep Mode The microcontroller can now switch the LIN transceiver into LIN Normal Mode via SPI to start communication Table 18 Action due to a LIN BUS Wake up SBC Mode SBC Mode after W...

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Page 95: ...ted If only WK1_EN WK2_EN are set while trying to go to SBC Sleep Mode then the SPI_FAIL flag will be set and the SBC will be changed into SBC Restart Mode WK_PUPD_CTRL normal configuration is possibl...

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Page 125: ...ollowing conditions in case the number of received SPI clocks is not 0 or 16 in case RO is LOW and SPI frames are being sent at the same time Downloaded from Arrow com Downloaded from Arrow com Downlo...

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Page 131: ...I LY A N D P R O D U C T R E G I S T E R S S T A T U S R E G I S T E R S Register Short Name Access Mode Address A6 A0 C O N T R O L R E G I S T E R S Downloaded from Arrow com Downloaded from Arrow...

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Page 175: ...om Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from...

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