TLE4997
User’s Manual
TLE4997 Programming
User’s Manual
12
v01_01, 2019-08
TADC
This register contains a 15bit unsigned raw temperature value.
STATUS
The content of the status register is shown in
.
Figure 3-11 Status Register
•
CRC ok has to be “1”, otherwise the DSP built-in self-test was failed and the device is defective
•
LOCKED must be ’0’ as long as the lockbits are not programmed. After setting the lockbits the lock can be
verified by refreshing the EEPROM content and checking this bit before the supply of the device is removed
or the interface is closed.
•
perr_adr has to be on address F
H
(“1111
B
”), otherwise it shows the first EEPROM address where the internal
parity check failed.
•
perr_more must be “0”, otherwise more than one EEPROM address has a parity error.
•
perr_col must be “0”, otherwise one or more EEPROM columns have a parity error.
•
HWver contains the actual silicon revision starting with 0 (=”000”). The latest version from 8’ manufacturing line
is version 3 (=”011”, availability from mid 2006 and released for productive use).
•
ROMSIG has to be 1F
H
, otherwise the DSP ROM is not valid and the device is defective.
DAC_SET
This register contains a 12 bit unsigned decimal value. When the DAC test bit is set, the value of this register is
used on the ratiometric output.
TEST
The content of the test register is shown in
. All bits are “0” after reset. All bits not described or used
shall be kept at “0”.
Figure 3-12 Test Register
•
“Margin zero on” is used to select the margin test mode. It is set to ‘1’ for testing the EEPROM threshold
voltages of cells programmed to ‘0’, and it is set to ‘0’ for testing the EEPROM threshold voltages of cells
programmed to ‘1’.
•
“FEC off” switches off the error correction of the EEPROM. This bit has to be set when reading the EEPROM
content.
•
“REF off” switches off the automatic (cyclic) refresh performed by the DSP to actualize the EEPROM registers
from the EEPROM cells. This bit has to be set when writing new values to the EEPROM registers.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB
RO
M
S
IG
4
p
e
rr_
m
o
re
LO
C
K
E
D
per
r_adr
0
CR
C
o
k
per
r_adr
1
per
r_adr
2
per
r_adr
3
HW
ve
r0
RO
M
S
IG
3
RO
M
S
IG
2
RO
M
S
IG
1
RO
M
S
IG
0
HW
ve
r1
HW
ve
r2
per
r_
col
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LSB
FE
C
o
ff
DA
C
te
st
D
SP
sto
p
RE
F
o
ff
D
SP
o
ff
0
0
0
0
0
0
0
0
0
0
0
MSB
