Infineon EiceDRIVER 6ED Series, Application Note

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6ED family - 2nd generation
Technical Description
Application Note 5 Rev. 1.3, 2014-03-23
AN-EICEDRIVER-6EDL04-1
List of Figures
Figure 1 Cross section of a FET in SOI-technology ........................................................................................... 8
Figure 2 Different reference systems for a) 6ED family
– 2
nd
generation b) many other 6channel gate drive IC9
Figure 3 Control input pin structure a) negative logic b) positive logic ............................................................. 10
Figure 4 Short pulse suppression (left: short ON pulse; right: short OFF pulse) a) and b): negative logic c)
and d): positive logic .......................................................................................................................... 11
Figure 5 Schematic of the structure of the /FAULT-pin .................................................................................... 11
Figure 6 Timing diagramm for ITRIP to FAULT propagation delay .................................................................. 12
Figure 7 Areas of operation .............................................................................................................................. 12
Figure 8 Structure of the lowside gate drive section ........................................................................................ 13
Figure 9 Structure of the lowside gate drive section ........................................................................................ 14
Figure 10 Bootstrap circuit for one halfbridge a) 6ED003L06-F2 and 6ED003L02-F2 b) others ....................... 14
Figure 11 Size of the bootstrap capacitor as a function of the switching frequency f
P
for driving IKD10N60R
according to equ. (2) with a voltage ripple of 0.1 V ............................................................................ 15
Figure 12 Internal structure of the ITRIP and RCIN sections ............................................................................. 16
Figure 13 Structure of a lowside UVLO .............................................................................................................. 17
Figure 14 Parasitic inductances in the layout ..................................................................................................... 19