Infineon EiceDRIVER 6ED Series Application Note Download Page 21

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6ED family - 2nd generation

Technical Description

Application Note

Rev. 1.3, 2014-03-23

AN-EICEDRIVER-6EDL04-1

Glossary and general terms

List of used parameters

4.1

General

big letters

Time constant parameters

small letters

Time varying parameters

italic letters

physical parameters

upright letters

components in circuits

Table 2

Used parameters

Parameter Description

Parameter

Description

area

p, P

power

b, B

flux density

r, R

resistance

capacitance

t, T

time, time intervals

d, D

duty cycle

v, V

voltage

frequency

w, W

energy

i, I

current



efficiency

l, L

inductance



capacitor

inductor

diode

resistor

integrated circuit

transformer

alternating current value

running variable

avg

average

input value

direct current value

max

maximum value

basis-emitter

min

minimum value

collector value

off

turn-off / off-state value

emitter value

turn-on / on-state value

gate value

out

output value

primary side value

pulsed

peak value

secondary side value

Summary of Contents for EiceDRIVER 6ED Series

Page 1: ...Industrial Power Control EiceDRIVER High voltage gate drive IC Application Note AN EICEDRIVER 6EDL04 1 Rev 1 3 2014 03 23 6ED family 2nd generation Technical description ...

Page 2: ...SPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies...

Page 3: ...FirstGPS of Trimble Navigation Ltd EMV of EMVCo LLC Visa Holdings Inc EPCOS of Epcos AG FLEXGO of Microsoft Corporation FlexRay is licensed by FlexRay Consortium HYPERTERMINAL of Hilgraeve Incorporated IEC of Commission Electrotechnique Internationale IrDA of Infrared Data Association Corporation ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION MATLAB of MathWorks Inc MAXIM of Maxim Integrate...

Page 4: ...2 Enable pin EN 10 3 3 Control output section FAULT 11 3 4 IC supply section 12 3 5 Gate drive section 13 3 5 1 Low side gate drive 13 3 5 2 High side section 13 3 5 3 Negative Transients at High Side Reference pin VSx 14 3 6 Bootstrapping 14 3 7 Protection 16 3 7 1 Overcurrent protection ITRIP 16 3 7 2 Failure reset RCin 16 3 7 3 Deadtime Shoot Through Prevention 17 3 7 4 Undervoltage Lockout UVL...

Page 5: ...ogic 11 Figure 5 Schematic of the structure of the FAULT pin 11 Figure 6 Timing diagramm for ITRIP to FAULT propagation delay 12 Figure 7 Areas of operation 12 Figure 8 Structure of the lowside gate drive section 13 Figure 9 Structure of the lowside gate drive section 14 Figure 10 Bootstrap circuit for one halfbridge a 6ED003L06 F2 and 6ED003L02 F2 b others 14 Figure 11 Size of the bootstrap capac...

Page 6: ...6ED family 2nd generation Technical Description Application Note 6 Rev 1 3 2014 03 23 AN EICEDRIVER 6EDL04 1 List of Tables Table 1 Members of 6ED family 2nd generation 7 Table 2 Used parameters 21 ...

Page 7: ...rol input HIN1 2 3 and LIN1 2 3 UVLO threshold Bootstrap diode Package Optimal for 6EDL04I06NT negative logic 12 1V 10 2V Yes DSO28 IGBT 6EDL04I06PT positive logic 12 1V 10 2V Yes DSO28 IGBT 6EDL04N06PT 6EDL04N02PR positive logic 8 9V 8 0V Yes DSO28 TSSOP28 MOSFET 6ED003L06 F2 6ED003L02 F2 negative logic 12 1V 10 2V No DSO28 TSSOP28 IGBT replacement of 1 st generation It is obvious that the 6ED fa...

Page 8: ...LOCOS process Thus there is no need for CMOS wells for preventing the latch up effect and reducing the chip size The small size of PN junctions inside the thin silicon film leads to higher switching speed lower leakage currents and consequently higher temperature stability In order to obtain a proper body contact for the thin SOI MOS transistor the channel doping is extended and connected to a com...

Page 9: ...s that the 6ED family 2 nd generation has another margin of 5 7 V with respect to COM The relevant maximum rating of 6ED family 2 nd generation in the datasheet on p 14 are The 6ED family 2 nd generation gives a maximum rating for VCC in respect to VSS 20 V The 6ED family 2 nd generation gives a maximum rating for COM in respect to VSS 5 7 V The 6ED family 2 nd generation give a maximum rating for...

Page 10: ...N 200 μA if applying a LOW signal An external additional pull up resistor can help to obtain a reliable and precise control signal B of Figure 3 presents the structure of positive logic The pull down resistor has a value of typical 5 k The input bias currents with ILIN IHIN 660 μA are therefore higher compared to the negative logic The input noise filter suppresses short pulses and prevents the dr...

Page 11: ... for this open drain pin The voltage at this pin is internally clamped to VCC as one can see in the internal structure according to Figure 5 The internal pull down FET has a typical resistance of RON FLT 61 The delay time from the triggering event to the change of status at the FAULT pin is tFLT 450 ns typically according to the timing diagram shown in Figure 6 FAULT 1 from uv detection VCC RON FL...

Page 12: ...hside supply before the IC gets into an operational state The levels of these parameters are either 11 7 V or 9 V depending on the individual type of the 6ED family It is recommended to have a margin of at least 1 V in respect to VCCUV and VBSUV in order to avoid unintended shut down caused by noise The IC shuts down the individual gate sections when the related supply voltage is below VCCUV or VB...

Page 13: ...upply voltage VCC of the IC via the reverse diodes of the FET This prevents the output pins from excessive pulse voltages which may be coupled into the gate track There is also an internal zener clamp of the push pull circuit between COM and VCC 3 5 2 High side section The high side gate drive section is shown in Figure 9 The control signal passes the high voltage level shift section and is stored...

Page 14: ...n also increase the pulse current through the external or internal bootstrap diode and may lead to damage The design target is therefore to avoid such negative transient voltage at all or to keep at least the absolute maximum ratings 3 6 Bootstrapping Bootstrapping is a common method of pumping charges from a low potential to a higher one With this technique a supply voltage for the floating highs...

Page 15: ...tor is mainly discharged by two effects The highside quiescent current and the gate charge of the transistor to be turned on The calculation of the bootstrap capacitor results in 2 with iQBS being the quiescent current of the highside section tP the switching period QG the total gate charge and vBS the voltage drop at the bootstrap capacitor within a switching period An additional margin of 20 is ...

Page 16: ...he comparator is low again This corresponds to a voltage level at the comparator of VIT TH VIT HYS 445 mV 70 mV 375 mV where VIT HYS 70 mV is the hysteresis of the ITRIP comparator RCIN IRCIN VZ 10 5V ITRIP SET DOMINANT LATCH S R Q INPUT NOISE FILTER VIT TH 0 445V Comp COM VSS VDD2 8V NMOS RON RCIN current source VSS VCC VCC to FAULT 6ED family 2nd generation RRCin CRCin VRCIN TH 5 2V VRCIN HYS 2 ...

Page 17: ...e drive sections The levels are VCCUV for the control side and VBSUV for the high side sections Please refer to the correct absolute level in respect to the individual type of the 6ED family Please refer to section 3 4 for further information In case of an UVLO shut down of an output section it is necessary to reach the start up levels of VCCUV and VBSUV again as descibed in section 3 4 The indepe...

Page 18: ...and the ext gate resistor Different cases for turn on and turn off must be considered because many designs use different resistors for turn on and turn off This leads to a specific distribution of losses in respect to the external gate resistor RGxx ext and the internal resistance of the output section 7 8 Both portions Pd2on and Pd2on together are the output section losses 3 The input sections ge...

Page 19: ...e IC Figure 14 shows these inductances and track loops VDC DBS 3 x 600V 1A VCC Low inductive shunt Small and short loops LOx HOx VSx COM VSS VBx RLim RSh CBS CDC Figure 14 Parasitic inductances in the layout First of all the gate tracks which connect the pins HOx and LOx with the according gate terminal of the power transistor and the tracks connecting the emitter source terminals of the power tra...

Page 20: ...nd the pin VS must also be small Otherwise there may be inductive voltage drops during the gate charging process of turn on which may result in spontaneous undervoltage lockout events at the high side section Finally the inductances of the DC link tracks can be partially cancelled if one places a low impedance film capacitor between the positive and negative rail closely to the transistor terminal...

Page 21: ... A area p P power b B flux density r R resistance C capacitance t T time time intervals d D duty cycle v V voltage f frequency w W energy i I current efficiency l L inductance C capacitor L inductor D diode R resistor IC integrated circuit TR transformer AC alternating current value i running variable avg average in input value DC direct current value max maximum value BE basis emitter min minimum...

Page 22: ...e KOA corporation Japan 2007 5 KOA corporation Flat chip thick film resistors general purpose RK73B Revision 10 11 2006 data sheet KOA corporation Japan 2006 6 IEC 60335 1 Household and similar electrical appliances Safety Part 1 General requirements Ed 4 2001 05 International Electrotechnical Commission Geneva Switzerland 2001 7 IEC 664 1 Insulation coordination for equipment within low voltage s...

Page 23: ...w w w i n f i n e o n c o m Published by Infineon Technologies AG AN EICEDRIVER 1 ...

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