6ED family - 2nd generation
Technical Description
Application Note
12
Rev. 1.3, 2014-03-23
AN-EICEDRIVER-6EDL04-1
Figure 6
Timing diagramm for ITRIP to FAULT propagation delay
3.4
IC supply section
The 6ED family
– 2
nd
generation supports the operation of IGBT as well as power MOSFET. There is a
considerable difference between both types of power transistors in respect of driving their gates. IGBT usually
have a gate threshold voltage
V
GE(th)
= 4.
5 V … 7 V, where power MOSFET have a gate threshold of
V
GS(th)
=
3
V … 4 V. As a consequence, MOSFET are usually driven sufficiently with a gate source voltage of
V
GS
= 10 V
without loosing conduction performance, where IGBT need a recommended gate emitter voltage of
V
GE
= 15 V.
This difference is considered in the two different undervoltage lockout (UVLO) levels of the 6ED family
– 2
nd
generation. The absolute maximum rating is in all cases
V
CC,max
= 20 V regardless of the undervoltage lockout
levels.
The supply voltage of the IC must reach initially at least a typical voltage of
V
CCUV+
and
V
BSUV+
, respectively for
the lowside and highside supply, before the IC gets into an operational state. The levels of these parameters are
either 11.7 V or 9 V depending on the individual type of the 6ED family. It is recommended to have a margin of
at least 1 V in respect to
V
CCUV+
and
V
BSUV+
in order to avoid unintended shut-down caused by noise. The IC
shuts down the individual gate sections, when the related supply voltage is below
V
CCUV-
or
V
BSUV-
. The levels
here are either 9.8 V or 8.1 V. This prevents the driven transistors from critically low gate voltage levels during
on-state and therefore from excessive power dissipation. Please refer to section 3.7.4 for further information.
Figure 7
Areas of operation
Figure 7Figure 8 shows the IC states and the correlated areas of operation concerning the supply voltages for
both the lowside supply voltage
v
CC
and the highside supply voltages
v
BS
. There is a forbidden area for supply
voltages above 20 V, because here the internal clamping structures begin to break through and the IC is
endangered to be damaged by locally excessive power dissipation.
0.1V
0.5V
v
ITRIP
v
FAULT
t
FLT
t
FLT
V
ITRIP
t
t
ON
OFF
ON
Recommended
Area
ON
Forbidden
Area
ON
ON
Recommended
Area
ON
OFF
20
17.5
v
CC
v
BS
t
IC STATE
V
CCMAX
, V
BSMAX
V
CCUV+
,
V
BSUV+
V
CCUV-
,
V
BSUV-
V
V
CCUV+
+1V
V
BSUV+
+1V
