CYTVII-B-E-2M-176-CPU Evaluation Board User Guide, Document Number. 002-29049 Rev. **
16
Connections and Settings
P6.6
PWM_M_3/PWM_2_N/TC_M_3_TR0/TC_2_TR1/SCB4_SEL3/TRIG_IN[8]/ADC[0]_6
JP10.5
P6.7
PWM_3/PWM_M_3_N/TC_3_TR0/TC_M_3_TR1/TRIG_IN[9]/ADC[0]_7
JP11.11
P7.0
PWM_M_4/PWM_3_N/TC_M_4_TR0/TC_3_TR1/SCB5_RX/SCB5_MISO/LIN4_RX/
CXPI0_RX/ADC[0]_8
JP12.3
P7.1
PWM_15/PWM_M_4_N/TC_15_TR0/TC_M_4_TR1/SCB5_TX/SCB5_SDA/SCB5_-
MOSI/LIN4_TX/CXPI0_TX/ADC[0]_9
JP12.6
P7.2
PWM_M_5/PWM_15_N/TC_M_5_TR0/TC_15_TR1/SCB5_RTS/SCB5_SCL/SCB5_CLK/
LIN4_EN/CXPI0_EN/ADC[0]_10
JP12.5
P7.3
PWM_16/PWM_M_5_N/TC_16_TR0/TC_M_5_TR1/SCB5_CTS/SCB5_SEL0/ADC[0]_11 JP10.10
P7.4
PWM_M_6/PWM_16_N/TC_M_6_TR0/TC_16_TR1/SCB5_SEL1/ADC[0]_12
JP10.9
P7.5
PWM_17/PWM_M_6_N/TC_17_TR0/TC_M_6_TR1/SCB5_SEL2/LIN10_RX/ADC[0]_13
JP10.12
P7.6
PWM_M_7/PWM_17_N/TC_M_7_TR0/TC_17_TR1/LIN10_TX/TRIG_IN[16]/ADC[0]_14
JP11.12
P7.7
PWM_18/PWM_M_7_N/TC_18_TR0/TC_M_7_TR1/LIN10_EN/TRIG_IN[17]/ADC[0]_15
JP11.9
P8.0
PWM_19/PWM_18_N/TC_19_TR0/TC_18_TR1/LIN2_RX/CAN0_0_TX
JP6.12
P8.1
PWM_20/PWM_19_N/TC_20_TR0/TC_19_TR1/LIN2_TX/CAN0_0_RX/TRIG_IN[14]/
ADC[0]_16
JP6.11
P8.2
PWM_21/PWM_20_N/TC_21_TR0/TC_20_TR1/LIN2_EN/TRIG_IN[15]/ADC[0]_17
JP2.8
P8.3
PWM_22/PWM_21_N/TC_22_TR0/TC_21_TR1/TRIG_DBG[0]/ADC[0]_18
JP11.10
P8.4
PWM_23/PWM_22_N/TC_23_TR0/TC_22_TR1/TRIG_DBG[1]/ADC[0]_19
JP9.9
P9.0
PWM_24/PWM_23_N/TC_24_TR0/TC_23_TR1/ADC[0]_20
JP9.12
P9.1
PWM_25/PWM_24_N/TC_25_TR0/TC_24_TR1/ADC[0]_21
JP9.11
P9.2
PWM_26/PWM_25_N/TC_26_TR0/TC_25_TR1/ADC[0]_22
JP9.14
P9.3
PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/ADC[0]_23
JP9.13
VCCD
VCCD
#NA
VDDA
VDDA
#NA
VDDD
VDDD
#NA
VDDIO VDDIO
#NA
VREFH VREFH
#NA
VREFL VREFL
#NA
VSSA
VSSA / VSSD / VSSIO/ Ground
JP1.19
XRES
XRES
#NA
Table 4-1. Device Port Pin Connections on Base Board
(continued)
Port
Pin
Pin Function
Access
Pin on
Base
Board
Summary of Contents for Cypress CYTVII-B-E-2M-176-CPU
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