CYTVII-B-E-2M-176-CPU Evaluation Board User Guide, Document Number. 002-29049 Rev. **
13
Connections and Settings
P17.3
PWM_58/PWM_59_N/TC_58_TR0/TC_59_TR1/PWM_H_3/SCB3_RTS/SCB3_SCL/
SCB3_CLK/
TRIG_IN[26]
JP4.5
P17.4
PWM_57/PWM_58_N/TC_57_TR0/TC_58_TR1/PWM_H_3_N/SCB3_CTS/SCB3_SEL0/
TRIG_IN[27]
JP4.11
P17.5
PWM_56/PWM_57_N/TC_56_TR0/TC_57_TR1/SCB3_SEL1
JP3.10
P17.6
PWM_M_4/PWM_56_N/TC_M_4_TR0/TC_56_TR1/SCB3_SEL2
JP3.8
P17.7
PWM_M_5/PWM_M_4_N/TC_M_5_TR0/TC_M_4_TR1
JP3.6
P18.0
PWM_M_6/PWM_M_5_N/TC_M_6_TR0/TC_M_5_TR1/PWM_H_0/SCB1_RX/
SCB1_MISO/FAULT_OUT_0/
ADC[2]_0
JP3.18
P18.1
PWM_M_7/PWM_M_6_N/TC_M_7_TR0/TC_M_6_TR1/PWM_H_0_N/SCB1_TX/
SCB1_SDA/SCB1_MOSI/FAULT_OUT_1/
ADC[2]_1
JP3.16
P18.2
PWM_55/PWM_M_7_N/TC_55_TR0/TC_M_7_TR1/PWM_H_1/SCB1_RTS/SCB1_SCL/
SCB1_CLK/ADC[2]_2
JP9.17
P18.3
PWM_54/PWM_55_N/TC_54_TR0/TC_55_TR1/PWM_H_1_N/SCB1_CTS/SCB1_SEL0/
TRACE_CLOCK/ADC[2]_3
#NA
P18.4
PWM_53/PWM_54_N/TC_53_TR0/TC_54_TR1/PWM_H_2/SCB1_SEL1/TRACE_-
DATA_0/ADC[2]_4
JP9.18
P18.5
PWM_52/PWM_53_N/TC_52_TR0/TC_53_TR1/PWM_H_2_N/SCB1_SEL2/TRACE_-
DATA_1/ADC[2]_5
JP12.4
P18.6
PWM_51/PWM_52_N/TC_51_TR0/TC_52_TR1/PWM_H_3/SCB1_SEL3/CAN1_2_TX/
TRACE_DATA_2/ADC[2]_6
JP11.6
P18.7
PWM_50/PWM_51_N/TC_50_TR0/TC_51_TR1/PWM_H_3_N/CAN1_2_RX/TRACE_-
DATA_3/ADC[2]_7
JP11.5
P19.0
PWM_M_3/PWM_50_N/TC_M_3_TR0/TC_50_TR1/TC_H_0_TR0/SCB2_RX/
SCB2_MISO/CAN1_3_TX/FAULT_OUT_2
JP7.9
P19.1
PWM_26/PWM_M_3_N/TC_26_TR0/TC_M_3_TR1/TC_H_0_TR1/SCB2_TX/
SCB2_SDA/SCB2_MOSI/CAN1_3_RX/
CXPI3_RX/FAULT_OUT_3
JP7.13
P19.2
PWM_27/PWM_26_N/TC_27_TR0/TC_26_TR1/TC_H_1_TR0/SCB2_RTS/SCB2_SCL/
SCB2_CLK/CXPI3_TX/
TRIG_IN[28]
JP6.5
P19.3
PWM_28/PWM_27_N/TC_28_TR0/TC_27_TR1/TC_H_1_TR1/SCB2_CTS/SCB2_SEL0/
CXPI3_EN/TRIG_IN[29]
JP6.10
P19.4
PWM_29/PWM_28_N/TC_29_TR0/TC_28_TR1/TC_H_2_TR0/SCB2_SEL1
JP3.4
P2.0
PWM_7/PWM_8_N/TC_7_TR0/TC_8_TR1/TC_H_4_TR0/SCB7_RX/SCB0_SEL1/
SCB7_MISO/LIN0_RX/
CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2]
#NA
P2.1
PWM_6/PWM_7_N/TC_6_TR0/TC_7_TR1/TC_H_5_TR0/SCB7_TX/SCB7_SDA/
SCB0_SEL2/SCB7_MOSI/
LIN0_TX/CAN0_0_RX/TRIG_IN[3]
JP1.4
P2.2
PWM_5/PWM_6_N/TC_5_TR0/TC_6_TR1/TC_H_6_TR0/SCB7_RTS/SCB7_SCL/
SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4]
JP1.6
P2.3
PWM_4/PWM_5_N/TC_4_TR0/TC_5_TR1/TC_H_7_TR0/SCB7_CTS/SCB7_SEL0/
LIN5_RX/TRIG_IN[5]
JP10.11
P2.4
PWM_3/PWM_4_N/TC_3_TR0/TC_4_TR1/PWM_H_4_N/SCB7_SEL1/LIN5_TX/
TRIG_IN[6]
JP8.8
Table 4-1. Device Port Pin Connections on Base Board
(continued)
Port
Pin
Pin Function
Access
Pin on
Base
Board
Summary of Contents for Cypress CYTVII-B-E-2M-176-CPU
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