CPU_45A-V3
CPU Board XMC4500 General Purpose
Hardware Description
Board User's Manual
21
Revision 1.0, 2014-01-10
2.8
RTC
The XMC4400 CPU has two power domains, the Core Domain and Hibernate Domain. The Core Domain
(VDDP pins) is connected to the VDD3.3 rail. An on-board LDO voltage regulator generates VDD3.3 (3.3 V)
from VDD5 (5 V).
The Hibernate Domain is powered via the auxiliary supply pin VBAT, which is supplied by either a 3 V coin cell
(size 1216, 1220, 1225) plugged into the battery holder (see Figure 19) or 3.3 V (VDD3.3) generated by the on-
board voltage regulator.
Battery
Holder
Battery.emf
Figure 19 Battery Holder for Coin Cell
The Real Time Clock (RTC) is located in the hibernate domain. The XMC4500 uses the HIB_IO_1 signal (active
low) to shut down the external LDO voltage regulator which generates the VDD3.3 (Core Domain). Even if the
Core Domain is not powered the Hibernate Domain will operate if VBAT is available. The RTC keeps running as
long as the Hibernate Domain is powered via the auxiliary supply VBAT. The RTC is capable to wake-up the
whole system from Hibernate mode by setting HIB_IO_1 to high.
With VDD3.3 power supply switched off and no coin cell supply the power in the capacitor connected to VBAT
will provide power to the hibernate domain for about 10 seconds (depending on which features in the hibernate
domain are enabled).
Core Domain
CPU
Internal OSC
Hibernate Domain
VBAT
32.768 kHz
XMC4500
VDDP
IFX1763
LDO
Voltage Reg.
VDD3.3
+
RTC
S
P
I
RTC.emf
Battery
12 MHz
External OSC
Hibernate
Control
HIBIO_1
EN
Figure 20 RTC
