Infineon Technologies CPU_45A-V3, User Manual

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CPU_45A-V3
CPU Board XMC4500 General Purpose
Hardware Description
Board User's Manual 16 Revision 1.0, 2014-01-10
2.5.3 Cortex Debug+ETM Connector (20-pin)
The CPU_45A-V3 board supports Serial Wire debug operation, Serial Wire viewer operation (via SWO
connection when Serial Wire debug mode is used) and Instruction Trace operation through the 20-pin Cortex
Debug+ETM Connector.
JTAG operation additionally would require the TDI (P0.7) signal. By default the TDI signal is disconnected from
the Cortex Debug Connectors by a not assembled resistor R410, because the pin P0.7 is used by the Actuator
boards connected to the ACT satellite connector.
cortex-20pin.emf
SWO / TDO / EXTa / TRACECTL
Cortex Debug+ETM
Connector (20-pin)
GNDDetect
SWDIO / TMS
SWDCLK / TCK
1 2
3 4
5 6
7 8
9 10
VCC
GND
GND
KEY
nRESET
11
12
13 14
15
16
17 18
19 20
NC/EXTb/TDI
TRACECLK
TRACEDATA[0]
TRACEDATA[1]
TRACEDATA[2]
TRACEDATA[3]
GND/Cap
GND/Cap
GND
GND
GND
Figure 13 Cortex Debug+ETM Connector (20-pin)
Table 5 Cortex Debug+ETM Connector (20 Pin)
Pin No. Signal Name Serial Wire Debug JTAG Debug
1 VCC +3.3 V +3.3 V
2 SWDIO / TMS Serial Wire Data I/O Test Mode Select
3 GND Ground Ground
4 SWDCLK / TCK Serial Wire Clock Test Clock
5 GND Ground Ground
6 SWO / TDO Trace Data OUT Test Data OUT
7 KEY KEY KEY
8 NC / TDI Not connected Test Data IN
9 GNDDetect Ground Detect Ground Detect
10 nRESET Reset (Active Low) Reset (Active Low)
11 GND/Cap Ground Ground
12 TRACECLK Trace Clock Trace Clock
13 GND/Cap Ground Ground
14 TRACEDATA[0] Trace Data 0 Trace Data 0
15 GND Ground Ground