LP2995
DDR Termination Regulator
General Description
The LP2995 linear regulator is designed to meet the JEDEC
SSTL-2 and SSTL-3 specifications for termination of DDR-
SDRAM. The device contains a high-speed operational am-
plifier to provide excellent response to load transients. The
output stage prevents shoot through while delivering 1.5A
continuous current and transient peaks up to 3A in the
application as required for DDR-SDRAM termination. The
LP2995 also incorporates a V
SENSE
pin to provide superior
load regulation and a V
REF
output as a reference for the
chipset and DDR DIMMS.
Patents Pending
Features
n
Low output voltage offset
n
Works with +5v, +3.3v and 2.5v rails
n
Source and sink current
n
Low external component count
n
No external resistors required
n
Linear topology
n
Available in SO-8, PSOP-8 or LLP-16 packages
n
Low cost and easy to use
Applications
n
DDR Termination Voltage
n
SSTL-2
n
SSTL-3
Typical Application Circuit
20039302
July 2003
LP2995
DDR
T
ermination
Regulator
71
Summary of Contents for DW9937S
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Page 22: ...MITSUMI I2 C BUS Control 5 Input 2 Output AV Switch MM1313 Equivalent Block Diagram 20 ...
Page 70: ...FSDM07652RB Package Dimensions TO 220F 6L Forming 68 ...
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Page 75: ...11 Terminal for External Connection Outline Drawing 73 ...
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