Index DW9937S, Service Manual

Page: 63 / 112

FSDM07652RB
Functional Description
1. 1. 1. 1.
Startup : In previous generations of Fairchild Power
Switches (FPS
TM
) the Vcc pin had an external start-up
resistor to the DC input voltage line. In this generation the
startup resistor is replaced by an internal high voltage current
source. At startup, an internal high voltage current source
supplies the internal bias and charges the external capacitor
(C
vcc
) that is connected to the Vcc pin as illustrated in
Figure 4. When Vcc reaches 12V, the FSDM07652RB
begins switching and the internal high voltage current source
is disabled. Then, the FSDM07652RB continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless Vcc goes below the
stop voltage of 8V.
Figure 4. Internal startup circuit
2. Feedback Control : FSDM07652RB employs current
mode control, as shown in Figure 5. An opto-coupler (such
as the H11A817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across the
Rsense resistor plus an offset voltage makes it possible to
control the switching duty cycle. When the reference pin
voltage of the KA431 exceeds the internal reference voltage
of 2.5V, the H11A817A LED current increases, thus pulling
down the feedback voltage and reducing the duty cycle. This
event typically happens when the input voltage is increased
or the output load is decreased.
2.1 Pulse-by-pulse current limit : Because current mode
control is employed, the peak current through the Sense FET
is limited by the inverting input of PWM comparator (Vfb*)
as shown in Figure 5. Assuming that the 0.9mA current
source flows only through the internal resistor (2.5R +R= 2.8
k
Ω
), the cathode voltage of diode D2 is about 2.5V. Since D1
is blocked when the feedback voltage (Vfb) exceeds 2.5V,
the maximum voltage of the cathode of D2 is clamped at this
voltage, thus clamping Vfb*. Therefore, the peak value of
the current through the Sense FET is limited.
2.2 Leading edge blanking (LEB) : At the instant the
internal Sense FET is turned on, there usually exists a high
current spike through the Sense FET, caused by primary-side
capacitance and secondary-side rectifier reverse recovery.
Excessive voltage across the Rsense resistor would lead to
incorrect feedback operation in the current mode PWM
control. To counter this effect, the FSDM07652RB employs
a leading edge blanking (LEB) circuit. This circuit inhibits
the PWM comparator for a short time (T
LEB
) after the Sense
FET is turned on.
Figure 5. Pulse width modulation (PWM) circuit
3. Protection Circuit : The FSDM07652RB has several self
protective functions such as over load protection (OLP), over
voltage protection (OVP) and thermal shutdown (TSD).
Because these protection circuits are fully integrated into the
IC without external components, the reliability can be
improved without increasing cost. Once the fault condition
occurs, switching is terminated and the Sense FET remains
off. This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, 8V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the
FSDM07652RB resumes its normal operation. In this
manner, the auto-restart can alternately enable and disable
the switching of the power Sense FET until the fault
condition is eliminated (see Figure 6).
8V/12V
3
Vref
Internal
Bias
Vcc
6
Vstr
I
start
Vcc good
V
DC
C
Vcc
4
OSC
Vcc Vref
I
delay
I
FB
V
SD
R
2.5R
Gate
driver
OLP
D1 D2
+
V
fb
*
-
Vfb
KA431
C
B
Vo
H11A817A
R
sense
SenseFET
61