WAFER-ULT3/ULT4 3.5" SBC
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LVDS
Low-voltage differential signaling (LVDS) is a dual-wire, high-speed
differential electrical signaling system commonly used to connect LCD
displays to a computer.
POST
The Power-on Self Test (POST) is the pre-boot actions the system
performs when the system is turned-on.
RAM
Random Access Memory (RAM) is volatile memory that loses data when
power is lost. RAM has very fast data transfer rates compared to other
storage like hard drives.
SATA
Serial ATA (SATA) is a serial communications bus designed for data
transfers between storage devices and the computer chipsets. The SATA
bus has transfer speeds up to 1.5 Gbps and the SATA II bus has data
transfer speeds of up to 3.0 Gbps.
S.M.A.R.T
Self Monitoring Analysis and Reporting Technology (S.M.A.R.T) refers to
automatic status checking technology implemented on hard disk drives.
UART
Universal Asynchronous Receiver-transmitter (UART) is responsible for
asynchronous communications on the system and manages the system’s
serial communication (COM) ports.
UHCI
The Universal Host Controller Interface (UHCI) specification is a
register-level interface description for USB 1.1 Host Controllers.
USB
The Universal Serial Bus (USB) is an external bus standard for
interfacing devices. USB 1.1 supports 12Mbps data transfer rates and
USB 2.0 supports 480Mbps data transfer rates.
VGA
The Video Graphics Array (VGA) is a graphics display system developed
by IBM.
Summary of Contents for WAFER-UTL3
Page 14: ...WAFER ULT3 ULT4 3 5 SBC Page 1 Chapter 1 1 Introduction...
Page 18: ...WAFER ULT3 ULT4 3 5 SBC Page 5 Figure 1 3 Connectors Solder Side...
Page 24: ...WAFER ULT3 ULT4 3 5 SBC Page 11 Chapter 2 2 Packing List...
Page 28: ...WAFER ULT3 ULT4 3 5 SBC Page 15 Chapter 3 3 Connectors...
Page 59: ...WAFER ULT3 ULT4 3 5 SBC Page 46 Chapter 4 4 Installation...
Page 82: ...WAFER ULT3 ULT4 3 5 SBC Page 69 Chapter 5 5 BIOS...
Page 117: ...WAFER ULT3 ULT4 3 5 SBC Page 104 Appendix A A Regulatory Compliance...
Page 119: ...WAFER ULT3 ULT4 3 5 SBC Page 106 Appendix B B BIOS Options...
Page 122: ...WAFER ULT3 ULT4 3 5 SBC Page 109 Appendix C C Terminology...
Page 126: ...WAFER ULT3 ULT4 3 5 SBC Page 113 Appendix D D Digital I O Interface...
Page 129: ...WAFER ULT3 ULT4 3 5 SBC Page 116 Appendix E E Watchdog Timer...
Page 132: ...WAFER ULT3 ULT4 3 5 SBC Page 119 Appendix F F Hazardous Materials Disclosure...