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DRAM Settings
The first chipset settings deal with CPU access to dynamic random
access memory (DRAM). The default timings have been carefully
chosen and should only be altered if data is being lost. Such a
scenario might well occur if your system had mixed speed DRAM
chips installed so that greater delays may be required to preserve the
integrity of the data held in the slower memory chips.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing.
The Choice: 2, 3
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle.
The Choice: 5/7, 6/8.
SDRAM RAS-to-CAS Delay
This field lets you insert a timing delay between the CAS and RAS
strobe signals, used when DRAM is written to, read from, or refreshed.
Fast gives faster performance; and Slow gives more stable
performance. This field applies only when synchronous DRAM is
installed in the system.
The Choice: 2, 3.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to
accumulate its charge before DRAM refresh, the refresh may be
incomplete and the DRAM may fail to retain data. Fast gives faster
performance; and Slow gives more stable performance. This field
applies only when synchronous DRAM is installed in the system.
The Choice: 2, 3.
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