1. Board Design > Other Interfaces
15
Tsi382 (BGA) Evaluation Board User Manual
60E2010_MA001_03
Integrated Device Technology
www.idt.com
1.5.2
System Clock Distribution
The following figure shows the distribution of the system clock on the Tsi382 evaluation board.
Figure 3: System Clock Distribution
1.6
Other Interfaces
1.6.1
JTAG Interface
To support debug and testing of device, JTAG access to the Tsi382 is available using a standard JTAG
header for Wiggler connection.
1.6.2
EEPROM Interface
A single EEPROM device socket is available for programming the Tsi382’s registers during startup.
The socket is in an 8-pin DIP format.
Ti
p
For more information about accessing the Tsi382 using JTAG, see the
JTAG Register Access
Software Application Note
.
ICS87604I
PCIe System
PCIe_REFCLK
PCI Bus
Connectors
Tsi382
PCI_CLK
CLKOUT[0:1]
PCI_INT_CLK[0]
PCI_EXT_CLK[0]
PCI Clock
Buffer
CY2305
PCI_FBK_CLK
PCI_CLK[0:3]
PLD
ICS557-01
Diff.
SMA
Input
Passive
Mux
(0r0 RES)
ANALOG
MUX
PCIe_SYS_CLK
PCIe_GEN_CLK
PCIe_BERT_CLK
PCIe_REF_CLK
(AC coupled)
Config
PCI_EXT_CLK[1]
Resistor Mux
for CPLD
PCI_INT_CLK[1]
