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2. Configurable Options > LEDs

31

Tsi382 (BGA) Evaluation Board User Manual

60E2010_MA001_03

Integrated Device Technology

www.idt.com

2.4.3

P1 x1 PCIe Finger Connector

The pin assignment for the finger connector is as per the PCIe standard. Note that the JTAG signals 
TDI and TDO are connected together on the board. 

2.5

LEDs

LEDs D2–D8 indicate voltage supplies that are present on the evaluation board. Depending on whether 
your board is powered from the PCIe slot or the ATX power connector, the LEDs will indicate the 
source of power for the board. 

Summary of Contents for Tsi382 LQFP

Page 1: ...alley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc Tsi382 BGA Evaluation Board User Manual 60E2010_MA001_0...

Page 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Page 3: ...Power Requirements 11 1 4 3 Power Sequencing 13 1 4 4 System Power Design 13 1 4 5 PCI Vaux PCI Auxiliary Support 14 1 5 Clock Management 14 1 5 1 PCI 14 1 5 2 System Clock Distribution 15 1 6 Other...

Page 4: ...si382 BGA Evaluation Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com 2 4 1 J1 J2 J36 J37 Connectors 30 2 4 2 J3 ATX Power Connector 30 2 4 3 P1 x1 PCIe Finger Connector 31...

Page 5: ...rd Schematics PCI Express Base Specification Revision 1 1 PCI Express CEM Specification Revision 1 1 PCI Express to PCI PCI X Bridge Specification Revision 1 0 Terms Revision History 60E2010_MA001_03...

Page 6: ...About this Document 6 Tsi382 BGA Evaluation Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com...

Page 7: ...10 Clock Management on page 14 Other Interfaces on page 15 Hardware Reset on page 16 Logic Analyzer Connectivity on page 17 1 1 Overview The key features of the Tsi382 evaluation board include the fol...

Page 8: ...ion Board Block Diagram EEPROM Tsi382 3 3V PCI 32 bit Connector Slot 0 PCI Power Management PCI Express Card Edge X1 PCIe LA Probe JTAG Header ATX Connectors EEPROM 1x SerDes SMA Points SerDes Path Re...

Page 9: ...slots operating at 25 33 50 or 66 MHz 1 2 2 IDSEL Signals IDSEL signals are connected in the following order Slot 0 R A connector top slot 150 ohms to AD16 Device 0 Slot 1 150 ohms to AD17 Device 1 S...

Page 10: ...er Management 1 4 1 Power Regulation The evaluation board s power regulation is implemented as follows Digital 3 3V power supply available from DC DC regulator or ATX supply Digital 1 2V switching reg...

Page 11: ...PCIe slots are a maximum of 25W slot Current limits are included in Table 4 The usage of the 12V supply provides access to the full 25W available from the system to the board The PCIe pinout design in...

Page 12: ...owing conditions summarize the power available for a single PCI card without external supply An efficiency of 85 is taken into account for switching regulators These limits can be exceeded in cases wh...

Page 13: ...er card The following list is a functional summary of the power design 1 Sequencing control over the following rails 3 3V PCI 3 3V Tsi382 I O PCIe AVDD 1 2V Tsi382 Core PCIe VDD 2 ATX 20 pin connector...

Page 14: ...ates the required PCI clock for all slots Slave When in slave mode an on board selectable 25 66 MHz clock generator is used On board resistor muxes are used to multiplex either Tsi382 s PCI clock or t...

Page 15: ...ader for Wiggler connection 1 6 2 EEPROM Interface A single EEPROM device socket is available for programming the Tsi382 s registers during startup The socket is in an 8 pin DIP format Tip For more in...

Page 16: ...The following list outlines the connections to GPIO External I O header J7 1 NC J7 2 GPIO0 J7 3 GPIO1 J7 4 GPIO2 J7 5 GPIO3 J7 6 Connected to ground LEDs D11 GPIO0 active led when driven low D1 GPIO1...

Page 17: ...y the in band message sent by the root complex No supporting hardware is necessary 1 8 Logic Analyzer Connectivity The serial buses have Midbus pads TMS818 probe for visibility of SerDes lines using a...

Page 18: ...1 Board Design Logic Analyzer Connectivity 18 Tsi382 BGA Evaluation Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com...

Page 19: ...e the following Switches on page 19 Shunt Jumpers on page 24 Debug Headers on page 26 Connectors on page 29 LEDs on page 31 2 1 Switches 2 1 1 DIP Switches Switches S1 to S6 combine four small slide s...

Page 20: ...2 Configurable Options Switches 20 Tsi382 BGA Evaluation Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com Figure 6 Switch Locations SW2 S3 S4 SW1 S5 S6 S1...

Page 21: ...requency Table 8 contains the clock frequency settings for S3 Table 7 S1 Settings Switch Number Description Default State On Off Setting 1 M66EN ON ON Connects M66EN to all cards OFF Forces M66EN high...

Page 22: ...LL is a 25 MHz oscillator 3 PLL select OFF ON PLL is bypassed OFF PLL is enabled External clock source is multiplied as per S3 setting 4 No function Table 10 S5 Settings Switch Number Description Defa...

Page 23: ...tch is used only when the Tsi382 evaluation board is powered up with a stand alone ATX power supply SW2 is used to reset the evaluation board When pushing the reset button the board is reset the same...

Page 24: ...ard User Manual 60E2010_MA001_03 Integrated Device Technology www idt com 2 2 Shunt Jumpers Shunt jumpers control special features on the evaluation board see Figure 7 These jumpers are explained in t...

Page 25: ...bypass the On Off push button to enable the ATX power supply 2 2 2 J21 Shunt Jumper J21 is used to force the Tsi382 into a special debug mode The Default State for this jumper is ON Table 12 J6 Shunt...

Page 26: ...on Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com 2 3 Debug Headers Debug headers are used to connect to signals on the evaluation board see Figure 8 This section provides...

Page 27: ..._03 Integrated Device Technology www idt com 2 3 1 J22 Tsi382 JTAG Table 13 J22 Pin Assignment Pin Number Signal Assignment Pin Location 1 TDO 2 NC 3 TDI 4 3 3V 5 NC 6 3 3V 7 TCK 8 NC 9 TMS 10 NC 11 N...

Page 28: ...ADs Table 14 J23 Pin Assignment Pin Number Signal Assignment Pin Location 1 PCIE_RXD_EDG_P0 2 GND 3 PCIE_RXD_EDG_N0 4 PCIE_TXD_EDG_P0 5 GND 6 PCIE_TXD_EDG_N0 7 N C 8 GND 9 N C 10 N C 11 GND 12 N C 13...

Page 29: ...s Connectors 29 Tsi382 BGA Evaluation Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com 2 4 Connectors Figure 9 Board Connector Locations Figure 10 P1 J2 Slot 0 J1 Slot 2 J37...

Page 30: ...pin assignments are as per the PCI standard for 32 bit connectors 2 4 2 J3 ATX Power Connector A standard ATX power supply can be used to power up the board when used stand alone not plugged into a PC...

Page 31: ...assignment for the finger connector is as per the PCIe standard Note that the JTAG signals TDI and TDO are connected together on the board 2 5 LEDs LEDs D2 D8 indicate voltage supplies that are presen...

Page 32: ...2 Configurable Options LEDs 32 Tsi382 BGA Evaluation Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com Figure 11 LED Locations D2 D8 D18...

Page 33: ...ates 5V is applied to the evaluation board D5 5VSB This indicates 5V is applied to the evaluation board through the ATX connector D6 3 3V This indicates 3 3V is applied to the evaluation board D7 12V...

Page 34: ...2 Configurable Options LEDs 34 Tsi382 BGA Evaluation Board User Manual 60E2010_MA001_03 Integrated Device Technology www idt com...

Page 35: ...mer products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for a...

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