IDT Tsi382 LQFP, User Manual

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2. Configurable Options > Debug Headers 28
Tsi382 (BGA) Evaluation Board User Manual
60E2010_MA001_03
Integrated Device Technology
www.idt.com
2.3.2 J23 Logic Analyzer PADs
Table 14: J23 Pin Assignment
Pin
Number Signal Assignment Pin Location
1 PCIE_RXD_EDG_P0
2 GND
3 PCIE_RXD_EDG_N0
4 PCIE_TXD_EDG_P0
5 GND
6 PCIE_TXD_EDG_N0
7 N/C
8 GND
9 N/C
10 N/C
11 GND
12 N/C
13 N/C
14 GND
15 N/C
16 N/C
17 GND
18 N/C
19 N/C
20 GND
21 N/C
22 N/C
23 GND
24 N/C
1
7
5
9
3
2
4
6
8
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24