In
te
g
ra
te
d
D
e
v
ic
e
T
e
c
h
n
o
lo
g
y
Qu
ic
k
s
ta
rt
Qu
ic
k
s
ta
rt
ADC
1
4
1
0
S
,
AD
C12
1
0
S
,
AD
C10
1
0
S
s
e
rie
s
Q
u
ic
k
s
ta
rt
R
e
v
.
06
—
2
J
u
ly
2
0
1
2
3
of
27
1. Overview of the ADC1410S, ADC1210S, ADC1010S demo board
1.1 ADC1410S series
Figure below presents the connections to measure ADC1410S.
Fig 1. ADC1410S series typical configuration set-up
P
RESENTED CONFIGURATION
. 2V
pp
input full scale
. Single Sine wave clock signal
. Input common mode from IC
. Binary ADC output
. SPI Mode
I
NPUT SIGNAL
. 2V
pp
sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
F
ILTER
. High-order
. Band pass
P
OWER SUPPLY
. I = 185 mA
. N.C.
. 3V
.GND
P
OWER SUPPLY
. I = 20 mA
.GND
.1.8V
LOGIC
ANALYZER
Output data
. DAV for synchronization
. D0 (LSB) to D13 (MSB)
C
LOCK SIGNAL
. sinewave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
SPI
MODULE
USB
OR
P
ARALLEL
