7
©2018 Integrated Device Technology, Inc.
March 7, 2018
9FGV1005 Register Descriptions and Programming Guide
1
To be able to read this info, you already need to know the device address.
2
These two bits show the configuration number 0–3 that will be loaded from OTP into registers at power up. When changing these bits
through I
2
C you instruct the chip to load another configuration from OTP. This is useful for switching between OTP configurations when in
I
2
C mode. This method is also used to step through each configuration for reading back OTP contents.
Block Diagram
Figure 3. 9FGV1005 Block Diagram
Equations
:
FVCO = FCRYSTAL × Feedback Divider (see register 0x1F).
FOUT0 = FOUT1 = FVCO / Integer Divider (see registers 0x21 and 0x22).
Limits
:
FCRYSTAL: 10MHz–40MHz
FVCO: 2300MHz–2600MHz
Integer Output Divider: 8–4095
Feedback Divider: 12–255
30
0x1E
[7..4]
0000
Reserved.
[3..0]
1010
Charge pump current, 0 to 750
μ
A with step of 50
μ
A.
31
0x1F
[7..0]
24-hex
PLL feedback divider value.
32
0x20
[7..0]
12-hex
Reserved.
33
0x21
[7..0]
18-hex
Integer output divider value, bits [7..0].
34
0x22
[7..4]
0000
Integer output divider value, bits [11..8].
[3..0]
0000
Reserved.
35
0x23
[7..0]
00-hex
Reserved.
36
0x24
[7..0]
21-hex
Reserved.
37
0x25
7
0
Reserved.
6
1
Enable Integer output divide: 0 = disabled, 1 = enabled.
5
1
Enable crystal frequency doubler: 0 = disabled, 1 = enabled.
[4..3]
00
Reserved.
2
1
Integer output divide enable: 0 = disabled, 1 = enabled.
[1..0]
01
Reserved.
Table 3. RAM Register Map (Cont.)
Register Address
Register Bit
Default
Function Description
Decimal
Hex
