5
©2018 Integrated Device Technology, Inc.
March 7, 2018
9FGV1005 Register Descriptions and Programming Guide
06
0x06
7
0
Reserved.
6
0
Behavior when OUT1 is unused: 0 = Logic “0”, 1 = High impedance (tri-state).
5
1
OUT1 LP-HCSL slew rate control: 0 = Slow, 1 = Fast.
4
1
OUT1 LP-HCSL impedance control: 0 = 85
Ω
differential, 1 = 100
Ω
differential.
[3..0]
0100
OUT1 LP-HCSL amplitude control: 650mVpp at 0000 – 950mVpp at 1111.
07
0x07
7
0
Reserved.
[6..4]
101
OUT1 LVDS common mode control: 8
μ
A at 000 – 11.5
μ
A at 111.
3
0
Reserved.
[2..0]
100
OUT1 LVDS amplitude control: 30
μ
A at 000 – 65
μ
A at 111.
08
0x08
[7..0]
03-hex
Reserved.
09
0x09
[7..0]
34-hex
Reserved.
10
0x0A
[7..0]
54-hex
Reserved.
11
0x0B
7
1
Enable OUT0: 0 = Disabled (unused), 1 = Enabled.
[6..4]
000
OUT0 configuration:
000 = LP-HCSL, Low-power HCSL.
001 = CMOS1, Single-ended CMOS on true output pin.
011 = LVDS.
100 = CMOS2, Single-ended CMOS on complementary output pin.
101 = CMOSD, Differential CMOS.
111 = CMOSP, Two single-ended CMOS outputs, in-phase.
010 and 110 are not used.
[3..2]
00
OUT0 power supply voltage: 00 = 01 = 1.8V, 10 = 2.5V, 11 = 3.3V.
[1..0]
11
Reserved.
12
0x0C
7
0
Reserved.
6
0
Behavior when OUT0 is unused: 0 = Logic “0”, 1 = High impedance (tri-state).
5
1
OUT0 LP-HCSL slew rate control: 0 = Slow, 1 = Fast.
4
1
OUT0 LP-HCSL impedance control: 0 = 85
Ω
differential, 1 = 100
Ω
differential.
[3..0]
0100
OUT0 LP-HCSL amplitude control: 650mVpp at 0000 – 950mVpp at 1111.
13
0x0D
7
0
Reserved.
[6..4]
101
OUT0 LVDS common mode control: 8
μ
A at 000 – 11.5
μ
A at 111.
3
0
Reserved.
[2..0]
100
OUT0 LVDS amplitude control: 30
μ
A at 000 – 65
μ
A at 111.
Table 3. RAM Register Map (Cont.)
Register Address
Register Bit
Default
Function Description
Decimal
Hex
