IDT 89HPES16T4G2, Preliminary User'S Manual

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IDT Configuration Registers
PES16T4G2 User Manual 8 - 27 January 28, 2013
Notes
PCIESCAP - PCI Express Slot Capabilities (0x054)
14 LBWSTS RW1C 0x0 Link Bandwidth Management Status. This bit is set to indicate
that either of the following have occurred without the link transition-
ing through the DL_Down state.
A link retraining initiated by setting the LRET bit in the PCIELCTL
register has completed.
The PHY has autonomously changed link speed or width to
attempt to correct unreliable link operation either through an
LTSSM time-out or a higher level process.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was not
indicated as an autonomous change.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in the upstream port.
15 LABWSTS RW1C 0x0 Link Autonomous Bandwidth Status. This bit is set to indicate
that either that the PHY has autonomously changed link speed or
width for reasons other than to attempt to correct unreliable link
operation.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was indi-
cated as an autonomous change.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in the upstream port.
Bit
Field
Field
Name
Type Default
Value
Description
0 ABP RWL 0x0 Attention Button Present. This bit is set when the Attention But-
ton is implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
1 PCP RWL 0x0 Power Control Present. This bit is set when a Power Controller
is implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
2 MRLP RWL 0x0 MRL Sensor Present. This bit is set when an MRL Sensor is
implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
3 ATTIP RWL 0x0 Attention Indicator Present. This bit is set when an Attention
Indicator is implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
4 PWRIP RWL 0x0 Power Indicator Present. This bit is set when an Power Indicator
is implemented for the port.
This bit is read-only and has a value of zero when the SLOT bit in
the PCIECAP register is cleared.
Bit
Field
Field
Name
Type Default
Value
Description