Notes
PES16T4G2 User Manual
vii
January 28, 2013
List of Figures
®
Figure 1.1
PES16T4G2 Architectural Block Diagram ..........................................................................1-2
Figure 1.2
PES16T4G2 Logic Diagram ...............................................................................................1-3
Figure 1.3
PES16T4G2 Port & Device Numbering ...........................................................................1-11
Figure 2.1
Fundamental Reset with Serial EEPROM Initialization ......................................................2-4
Figure 2.2
Fundamental Reset Using RSTHALT to Keep Device in Quasi-Reset State .....................2-5
Figure 2.3
Power Enable Controlled Reset Output Mode Operation ..................................................2-7
Figure 2.4
Power Good Controlled Reset Output Mode Operation .....................................................2-8
Figure 3.1
Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH=0x4) .......................3-1
Figure 3.2
Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH=0x2) .......................3-2
Figure 3.3
PES16T4G2 ASPM Link Sate Transitions .........................................................................3-7
Figure 5.1
SMBus Interface Configuration Examples .........................................................................5-1
Figure 5.2
Single Double Word Initialization Sequence Format ..........................................................5-3
Figure 5.3
Sequential Double Word Initialization Sequence Format ...................................................5-4
Figure 5.4
Configuration Done Sequence Format ..............................................................................5-4
Figure 5.5
Slave SMBus Command Code Format ............................................................................5-12
Figure 5.6
CSR Register Read or Write CMD Field Format ..............................................................5-13
Figure 5.7
Serial EEPROM Read or Write CMD Field Format ..........................................................5-15
Figure 5.8
CSR Register Read Using SMBus Block Write/Read Transactions with PEC Disabled ..5-16
Figure 5.9
Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................5-16
Figure 5.10
CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........5-16
Figure 5.11
Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........5-17
Figure 5.12
Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........5-17
Figure 5.13
CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....5-17
Figure 6.1
PES16T4G2 Power Management State Transition Diagram .............................................6-1
Figure 7.1
Hot-Plug on Switch Downstream Slots Application ............................................................7-1
Figure 7.2
Hot-Plug with Switch on Add-In Card Application ..............................................................7-2
Figure 7.3
Hot-Plug with Carrier Card Application ..............................................................................7-2
Figure 7.4
PES16T4G2 Hot-Plug Event Signalling .............................................................................7-5
Figure 8.1
Port Configuration Space Organization .............................................................................8-2
Figure 9.1
Diagram of the JTAG Logic ................................................................................................9-1
Figure 9.2
State Diagram of PES16T4G2’s TAP Controller ................................................................9-2
Figure 9.3
Diagram of Observe-only Input Cell ...................................................................................9-4
Figure 9.4
Diagram of Output Cell ......................................................................................................9-5
Figure 9.5
Diagram of Bidirectional Cell ..............................................................................................9-5
Figure 9.6
Device ID Register Format .................................................................................................9-7
Summary of Contents for 89HPES16T4G2
Page 10: ...IDT Table of Contents PES16T4G2 User Manual iv January 28 2013 Notes...
Page 12: ...IDT List of Tables PES16T4G2 User Manual vi January 28 2013 Notes...
Page 14: ...IDT List of Figures PES16T4G2 User Manual viii January 28 2013 Notes...
Page 18: ...IDT Register List PES16T4G2 User Manual xii January 28 2013 Notes...
Page 30: ...IDT PES16T4G2 Device Overview PES16T4G2 User Manual 1 12 January 28 2013 Notes...
Page 48: ...IDT Link Operation PES16T4G2 User Manual 3 10 January 28 2013 Notes...
Page 68: ...IDT SMBus Interfaces PES16T4G2 User Manual 5 18 January 28 2013 Notes...
Page 72: ...IDT Power Management PES16T4G2 User Manual 6 4 January 28 2013 Notes...
Page 140: ...IDT Configuration Registers PES16T4G2 User Manual 8 62 January 28 2013 Notes...