IDT 89EBPES24T3G2 Manual Download Page 35

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VDDCORE

VDDPEA

VDDPETA

VDDIO

VDDPEHA

Thu Jan 17 16:47:05 2008

SHEET 12 OF 12

1.0

18-657-000

D Huang

2008

K Leung / T Tran

SCH-00146

89EBPES24T3G2

A3 B7 C6 V9 V3

V18 V17 V16 V15 V12

U9 U3

U18 U17 U16 U15 U12

U1 T9 T8

T6 T5 T4 T3 T2

T18 T17 T16 T15 T14

T13

T12 T11 T10

R18

P18

P1 N7 N6

N18 N17 N16 N14 N13

N1 M3

M16 M13

L16

K16

K11

J16

J11

H16

H11

G18

G17

G16

G11

F16

F13

F12

F11

E16

D18

D17

D16

C16

B16

A16

A5 A4

A15

A11

N10

M10

L13

L10

K13

K12

N12

M12

L12

J13

J12

N11

M11

L11

H13

H12

G13

G12

B10

A18

A17

A14

A13

A10

R17

R16

R15

R12

P17

P16

P15

P12

N15

K14

K10

J10

H10

G15

G14

G10

F10

E13

E12

E11

E10

D15

D14

C100

C151

C156

C146

C155

C150

C168

C171

C165

C188

C187

C189

C70

C75

C80

C85

C90

C117

C122

C69

C74

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C94

C99

C104

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C83

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C67

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C102

C106

C110

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C81

C86

C91

C96

C101

C105

C109

C113

C118

C123

C127

C132

C137

C147

C142

C157

C152

C160

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C169

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C176

C131

C136

C141

C130

C135

C140

C145

C129

C134

C139

C149

C144

C154

C159

C162

C128

C133

C138

C143

C148

C153

C158

C161

C164

C167

C170

C173

C175

C177

C178

C179

C180

C181

C182

C183

C184

C185

C186

C95

89HPES24T3G2

- POWER

0.1UF

1.0UF

0.1UF

1.0UF

0.1UF

47UF

1.0UF

47UF

1.0UF

47UF

0.1UF

TITLE

DRAWING

NO.

AUTHOR

CHECKED

SIZE

REV.

FAB P/N

6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138

CONFIDENTIAL

PROPERTY

OF INTEGRATED

DEVICE

TECHNOLOGY,

INC.

89HPES24T3G2

(3 of 3)

VSS101

VSS100

VSS99

VSS98

VDDIO10

VSS97

VDDPEA14

VDDPEA13

VDDIO9

VDDIO8

VSS96

VSS95

VSS94

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VSS14

VSS13

VSS12

VSS11

VSS10

VSS9

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VSS6

VSS5

VSS4

VSS3

VSS2

VSS1

VSS0

VDDPETA12

VDDPETA11

VDDPETA10

VDDPETA9

VDDPETA8

VDDPETA7

VDDPETA6

VDDPETA5

VDDPETA4

VDDPETA3

VDDPETA2

VDDPETA1

VDDPEHA10

VDDPEHA9

VDDPEHA8

VDDPEHA7

VDDPEHA6

VDDPEHA5

VDDPEHA4

VDDPEHA3

VDDPEHA2

VDDPEHA1

VDDPEA12

VDDPEA11

VDDPEA10

VDDPEA9

VDDPEA8

VDDPEA7

VDDPEA6

VDDPEA5

VDDPEA4

VDDPEA3

VDDPEA2

VDDPEA1

VDDIO7

VDDIO6

VDDIO5

VDDIO4

VDDIO3

VDDIO2

VDDIO1

VDDCORE48

VDDCORE47

VDDCORE46

VDDCORE45

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VDDCORE14

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VDDCORE10

VDDCORE9

VDDCORE8

VDDCORE7

VDDCORE6

VDDCORE5

VDDCORE4

VDDCORE3

VDDCORE2

VDDCORE1

+2.5V_VDDHA

+1.0V_VDDA

+1.0V_CORE

+1.0V_VDDA

+2.5V_VDDHA

+1.0V_VDDTA

+1.0V_CORE

STIFF_6P

3_3VIO

3_3V

+1.0V_VDDTA

3_3VIO

Summary of Contents for 89EBPES24T3G2

Page 1: ...lver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2008 Integrated Device Technology Inc IDT 89EBPES24T3G2 Evaluation Board Manual E...

Page 2: ...ure Analysis be performed LIFE SUPPORT POLICY Integrated Device Technology s products are not authorized for use as critical components in life support devices or systems unless a specific written agr...

Page 3: ...er 2 2 PCI Express Analog Power Voltage Converter 2 2 PCI Express Transmitter Analog Power Voltage Converter 2 2 Core Logic Voltage Converter 2 2 3 3V I O Voltage Regulator 2 2 Power up Sequence 2 3 R...

Page 4: ...IDT Table of Contents EB24T3G2 Eval Board Manual ii January 21 2008 Notes...

Page 5: ...am Reset Selection 2 3 Table 2 5 Boot Configuration Vector Signals 2 4 Table 2 6 Boot Configuration Vector Switches S7 S8 ON 0 OFF 1 2 4 Table 2 7 Slave SMBus Interface Connector 2 5 Table 2 8 EEPROM...

Page 6: ...IDT List of Tables EB24T3G2 Eval Board Manual iv January 21 2008 Notes...

Page 7: ...Notes EB24T3G2 Eval Board Manual v January 21 2008 List of Figures Figure 1 1 Function Block Diagram of the EB24T3G2 Eval Board 1 1...

Page 8: ...IDT List of Figures EB24T3G2 Eval Board Manual vi January 21 2008 Notes...

Page 9: ...PCIe ports slots The EB24T3G2 board is designed to function as an add on card to be plugged into a x8 PCIe slot available on a motherboard hosting an appropriate root complex and microprocessor s The...

Page 10: ...4 pin header SMBUS Master Interface connected to the Serial EEPROMs through I O expander Attention button for each downstream port to initiate a hot swap event on each port Four pin connector for opt...

Page 11: ...between a PCI Express upstream port and down stream ports or peer to peer switching between downstream ports The EB24T3G2 has two PCI Express downstream ports accessible through two x8 connectors Bot...

Page 12: ...connector attached to J4 The external power supply provides 12V to the EB24T3G2 as described in Table 2 3 The 5V is unused PCI Express Analog High Power Voltage Converter A DC DC converter U18 provid...

Page 13: ...is is triggered by hardware while the device is powered on Warm Reset can be initiated by two methods Pressing a push button switch S1 located on EB24T3G2 board The host system board IO Controller Hub...

Page 14: ...Note The SMBus signals to the PCI Express edge connector is disabled by default To enable them place 0 ohm resistors at locations R160 and R161 Signal Description CCLKDS Common Clock Downstream The a...

Page 15: ...PCA9555 and a serial EEPROM 24LC512 Four I O Expanders are used as the interface for the onboard hot plug controllers MIC2591B The lower three bits of the bus address for the I O Expander0 1 2 4 are...

Page 16: ...ention Buttons The PES24T3G2 features three attention buttons shown in 2 10 Each button corresponds to a partic ular port and is used to initiate hot swapping events JTAG Connector J5 Pin Signal Direc...

Page 17: ...ed 2 3 Port 4 12V source from Upstream port Default 1 2 Port 4 12V source from hot plug controller W16 Header 2 3 Shunted 2 3 Port 2 3 3V source from Upstream port Default 1 2 Port 2 3 3V source from...

Page 18: ...Ground GND Ground 5 SMCLK SMBus clock JTAG2 TCK Test Clock JTAG i f clk i p 6 SMDAT SMBus Data JTAG TDI Test Data Input 7 GND Ground JTAG TDO Test Data Output 8 3 3V 3 3V power JTAG TMS Test Mode Sele...

Page 19: ...28 PETn3 pair Lane 3 GND Ground 29 GND Ground PERp3 Receiver differential 30 RSVD Reserved PERn3 pair Lane 3 31 PRSNT2 Hot Plug presence detect GND Ground 32 GND Ground RSVD Reserved 33 PETp4 Transmit...

Page 20: ...IDT Installation of the EB24T3G2 Eval Board EB24T3G2 Eval Board Manual 2 10 January 21 2008 EB24T3G2 Board Figure Slot 2 Slot 4 S6 S7 S8...

Page 21: ...ate a configuration file into an EEPROM programmable data structure This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES24T3G2 and then to populat...

Page 22: ...IDT Software for the EB24T3G2 Eval Board EB24T3G2 Eval Board Manual 3 2 January 21 2008 Notes...

Page 23: ...Notes EB24T3G2 Eval Board Manual 4 1 January 21 2008 Chapter 4 Schematics Schematics...

Page 24: ...SHEET DESCRIPTION Thu Jan 17 16 48 53 2008 PCB 0148R01 1 0 INITIAL RELEASE 2008 01 17 T TRAN B 18 657 000 1 0 D Huang SCH 00146 2008 K Leung T Tran SHEET 1 OF 12 89EBPES24T3G2 6 A TITLE CHECKED BY DCN...

Page 25: ...R1 3 2 1 W3 3 2 1 W2 3 2 1 W1 4 3 2 1 J4 3 2 1 W4 R1 R2 R4 4 5 1 3 2 U2 4 3 2 1 S1 8 7 2 5 6 4 3 1 U3 DS1 R5 DS2 R8 RED 10UF 47UF 25V 25V 25V 1 1 21K 10UF 10UF 5 WHT 330 10K 10K 5 0 PERST_N RESET POWE...

Page 26: ...665 1 665 10UF 10UF 0 YEL 10UF 6 5A RED 10K 4 64K RED 10UF DNP NA DNP NA NA DNP DNP DNP DNP 10UF 10UF 2 0K 10UF 10UF 10UF 10K 10UF 1 0UF 0 015UF REG_1V0_VDDA 0 015UF RED 0 1UF 1 0UF 1 0UF YEL REG_1V0_...

Page 27: ...3 49 9 49 9 REF_TESTOUT_CLKN SM0805 P0_REFCLKN 5 10K 33 BRD_T_CLKN 49 9 49 9 49 9 CONNSMA 1 475 1 49 9 YEL 11 9 10 10 9 11 9 6 8 8 11 5 1 P0_REFCLKP 5 6 CONNSMA ONBRD_REFCLKN ONBRD_REFCLKP P4_REFCLKP...

Page 28: ...9 5 11 11 5 11 5 10 8 4 6 5 9 10 6 9 2 7K DNP DNP 5 NA DNP DNP DNP NA NA 2 7K DNP DNP NA NA 10K 5 DNP 0 10 NA P2_WAKE_N 10K 4 6 P2_PWRGDN M_IOINTN0 M_SDA P4_LINKUPN 10K 10K M_IOINTN0 0 1UF 5 P4_APN 10...

Page 29: ...4_PFN P4_PWRGDN P4_VAUX 0 01UF 0 01UF 1 10K 1 23 2K 110K 0 0 0 022UF 0 1UF 0 1UF DNP 10K 10K 10K P2_PEP P2_F_ON 23 2K 1 1 110K 0 01UF 0 01UF 0 0 0 0 1UF 0 1UF DNP 10K 10K 10K 10K 5 RED 330 5 RED P4_IN...

Page 30: ...SENSE 5 15 P4_3VOUT P4_12VSENSE 12V_DS 5 0 02 0 022UF P2_12VOUT 2 P2_12VGATE 2 6800PF P2_12VSENSE 12V_DS P2_12V P2_3VSENSE P2_3VGATE PMOSFET P2_3_3V P2_VAUX P2_PCIE_3_3AUX P4_VAUX P4_12V P4_3_3V 0 02...

Page 31: ...P0_PETN0 P0_PETP0 P0_PETN1 P0_PETP1 P0_PETN2 P0_PETP2 P0_PETN3 P0_PETP3 P0_REFCLKN P0_REFCLKP PERST_N PORT 0 UPSTREAM EDGE CONN P0_ACTIVEN P0_LINKUPN DNP DNP DNP GRN GRN 5 330 330 5 25V P0_WAKE_N P0_...

Page 32: ...P2_PERST_N M_PERSTN 10UF 10UF 10UF 10UF 9 5 5 5 5 4 6 5 9 5 4 4 11 10 8 11 10 4 8 11 11 10 2 P2_PERST_N VERT OPEN P2_REFCLKP P2_REFCLKN 5 5 5 1K 11 11 11 11 11 P2_PETP3 P2_PETN3 P2_PETP0 P2_PETN0 P2_P...

Page 33: ...STN 5 330 DNP GRN DNP M_SSMBCLK P4_12V P4_PCIE_3_3AUX 10UF 25V 25V 10UF 10UF 10UF 11 4 4 10 11 2 11 9 4 8 11 11 11 11 11 5 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 4 11 9 8 P4_REFCL...

Page 34: ...ERP3 P4_PERP1 P4_PERP0 P4_PERN3 P4_PERN2 P4_PERN0 P2_PERN2 P2_PERP2 P2_PERN1 P2_PERP1 P2_PERP0 P2_PERP3 P2_PERN0 P0_PERP2 P0_PERP1 P0_PERP0 P0_PERN3 P0_PERN1 P0_PERN0 P0_PERN4 P0_PERP5 P0_PERN5 P0_PER...

Page 35: ...UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF...

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