IDT 89EBPES24T3G2, Manual

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IDT Installation of the EB24T3G2 Eval Board
EB24T3G2 Eval Board Manual 2 - 5 January 21, 2008
Notes .
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.
Initiation of any SMBus transaction other than those listed above produces undefined results. See the
SMBus 2.0 specification for a detailed description of the following transactions:
– Byte and Word Write/Read
– Block Write/Read
SMBus Master Interface
Connected to the master SMBus interface are four 16-bit I/O Expanders (PCA9555) and a serial
EEPROM (24LC512). Four I/O Expanders are used as the interface for the onboard hot-plug controllers
(MIC2591B). The lower three bits of the bus address for the I/O Expander0/1/2/4 are fixed as 0x0, 0x1, 0x2
and 0x4, respectively.
The seven bits address for the selected EEPROM device is
0b1010_000
by default and the lower
three bit is configurable using switch S8 as described in 2.8.
Slave SMBus Interface Connector J8
Pin Signal
1 N/C
2 SCL
3 GND
4 SDA
Table 2.7 Slave SMBus Interface Connector
S8[3] S8[4] S8[5] Bus Address
OFF OFF OFF 0b111
OFF OFF ON 0b110
OFF ON OFF 0101
OFF ON ON 0b100
ON OFF OFF 0b011
ON OFF ON 0b010
ON ON OFF 0b001
ON ON ON 0b000 (Default)
Table 2.8 EEPROM SMBus Address Setting