IDT 89EBPES24T3G2, Manual

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Notes
EB24T3G2 Eval Board Manual 2 - 1 January 21, 2008
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Chapter 2
Installation of the EB24T3G2
Eval Board
EB24T3G2 Installation
This chapter discusses the steps required to configure and install the EB24T3G2 evaluation board. All
available DIP switches and jumper configurations are explained in detail.
The primary installation steps are:
1. Configure jumper/switch options suitable for the evaluation or application requirements.
2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board.
3. Make sure that the host system (motherboard with root complex chipset) is powered off.
4. Insert the evaluation board into the host system.
5. Apply power to the host system.
The EB24T3G2 board is typically shipped with all jumpers and switches configured to their default
settings. In most cases, the board does not require further modification or setup.
Hardware Description
The PES24T3G2 is a 24-lane, 3-port PCI Express® switch. It is a peripheral chip that performs PCI
Express based switching with a feature set optimized for high performance applications such as servers
and storage. It provides fan-out and switching functions between a PCI Express upstream port and down-
stream ports or peer-to-peer switching between downstream ports.
The EB24T3G2 has two PCI Express downstream ports, accessible through two x8 connectors. Both
ports are capable of negotiating a x1, x2, x4, and x8 link width. All endpoint cards connected to the
PES24T3G2 must support one of these link widths.
Basic requirements for the board to run are:
– Host system with a PCI Express root complex supporting at least x8 configuration through a PCI
Express x8 or larger slot.
– x1, x2, x4 or x8 PCI Express Endpoint Cards.
Reference Clocks
The PES24T3G2 requires a differential reference clock. The EB24T3G2 derives this clock from a
common source which is user-selectable. The common source can be either the host system’s reference
clock or it can be the onboard clock generator. Selection is made by stuffing resistors as in Table 2.1.
The source for the onboard clock is the ICS841484 clock generator device (U4) connected to a 25MHz
oscillator (Y1). When using the onboard clock generator, the output frequency is fixed at 100MHz, therefore
FSEL0 (S7, bit 8) is On as the default setting.
Clock Configuration Stuffing Option
W6 and W7 Clock Source
Pins 2 and 3 Onboard Reference Clock – Use onboard clock generator
Pins 1 and 2 Upstream Reference Clock – Host system provides clock (Default)
Table 2.1 Clock Source Selection