ICS SB586TCP/166, Product Manual

Page: 39 / 128

PCI LOCAL BUS SIGNAL DESCRIPTIONS
The PCI Local Bus signals are described below and may be
categorized into the following functional groups:
•
System Pins
•
Address and Data Pins
•
Interface Control Pins
•
Arbitration Pins (Bus Masters Only)
•
Error Reporting Pins
•
Interrupt Pins (Optional)
•
Cache Support Pins (Optional)
•
64-Bit Bus Extension Pins (Optional)
•
JTAG/Boundary Scan Pins (Optional)
A # symbol at the end of a signal name indicates that the active state
occurs when the signal is at a low voltage. When the # symbol is ab-
sent, the signal is active at a high voltage.
The following are descriptions of the PCI Local Bus signals.
ACK64# (optional)
Acknowledge 64-bit Transfer, when actively driven by the device that has
positively decoded its address as the target of the current access, indicates
the target is willing to transfer data using 64 bits. ACK64# has the same timing
as DEVSEL#.
AD[31::00]
Address and Data are multiplexed on the same PCI pins. A bus transaction
consists of an address phase followed by one or more data phases. During
the address phase, AD[31::00] contain a physical address (32 bits). During
data phases, AD[07::00] contain the least significant byte (lsb) and AD[31::24]
contain the most signficant byte (msb).
AD[63::32] (optional)
Address and Data are multiplexed on the same pins and provide 32 additional
bits. During an address phase (when using the DAC command and when
REQ64# is asserted), the upper 32 bits of a 64-bit address are transferred;
PCI REFERENCE
TECHNICAL REFERENCE 2-15