5.2.4 INT Mask Control Register
The INT mask control register is presented as following table. The detail
function for these control register is described as below.
Table 5-6: INT mask control Register
(Read/Write): wBase+5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 0 0 0 0 0 EN1
EN0
EN0=0
Æ
disable INT0 to be an interrupt signal (default)
EN0=1
Æ
enable INT0 to be an interrupt signal
EN1=0
Æ
disable INT1 to be an interrupt signa (default)
EN1=1
Æ
enable INT1 to be an interrupt signal
The following is the partial programs for DOS C development environment
enable or disable interrupt function. For more information, please refer to the
DOS demo program demo1.c .
outportb(wBase+5,0); // disable all interrupts
outportb(wBase+5,1); // enable interrupt of INT0
outportb(wBase+5,2); // enable interrupt of INT1
outportb(wBase+5,3); // enable all two channels of interrupt
5.2.5 Aux Status Register
Based on the auxiliary status register, Aux0 (bit 0) and Aux 1(bit 1) stand as
INT0 and INT1 signal respectively. Aux2~3 (bit 2~3) represents the control
register of the EEPROM and Aux4~7 (bit 4~7) depicts the Aux-ID. Generally, the
Aux 0~1 are used as interrupt sources. Interrupt service has to check this
register to start service routing.
Table 5-7: AUX Status Register
(Read/Write): wBase+7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Aux7 Aux6 Aux5 Aux4 Aux3 Aux2 Aux1 Aux0
PISO-DA2/DA2U User Manual (Ver.2.7, Mar. 2012, PMH-020-27)
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