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SECTION 3
CIRCUIT DESCRIPTION
3 - 1
3-1 RECEIVER CIRCUITS
3-1-1 ANTENNA SWITCHING CIRCUIT
The antenna switching circuit functions as a low-pass filter
while receiving and as resonator circuit while transmitting.
The circuit does not allow transmit signals to enter receiver
circuits.
Received signals enter the MAIN unit from the antenna con-
nector and pass through the low-pass filter (L1–L3, C1–C5,
C7). The signals are then applied to the RF circuit via the
antenna switching circuit (D1, L4, L25).
3-1-2 RF CIRCUIT
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
a tunable bandpass filter (D2, L5) where the object signals
are led to the RF amplifier circuit (Q1).
The amplified signals at Q1 are applied to the 2-stage tun-
able bandpass filter (D3, D4, L6, L7) to suppress unwanted
signals and improve the selectivity. The signals are then
applied to the 1st mixer circuit.
D2–D4 employ varactor diodes, that are controlled by the
PLL lock voltage, to track the band pass filters.
3-1-3 1ST MIXER AND 1ST IF CIRCUITS
The 1st mixer circuit converts the received signal to a fixed
frequency of the 1st IF signal with a 1st LO (VCO output) fre-
quency. By changing the 1st LO frequency, only the desired
frequency will be passed through a pair of crystal filters at
the next stage of the mixer.
The signals from the RF circuit are mixed with the VCO sig-
nals at the 1st mixer circuit (Q2) to produce a 30.85 MHz 1st
IF signal.
The 1st IF signal is applied to a pair of crystal filters (FI1) to
suppress out-of-band signals and is then amplified at the IF
amplifier (Q3). The amplified signal is applied to the 2nd
mixer circuit (IC1).
3-1-4 2ND IF AND DEMODULATOR CIRCUITS
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double superheterodyne system (which converts
receive signals twice) improves the image rejection ratio and
obtains stable receiver gain.
The FM IF IC (IC1) contains the 2nd local oscillator, 2nd
mixer, limiter amplifier, quadrature detector, and noise
detector circuits, etc.
The 1st IF signal from Q3 is applied to the 2nd mixer section
of IC1 (pin 16), and is mixed with a 30.4 MHz 2nd LO signal
generated at the PLL circuit by doubling the reference fre-
quency (15.2 MHz) to produce a 450 kHz 2nd IF signal.
The 2nd IF signal from IC1 (pin 3) is passed through the
ceramic filter (FI2), where unwanted signals are sup-
pressed, and is then applied to the 2nd IF and limiter ampli-
fiers in IC1 (pin 5). The signal is applied to the FM detector
section in IC1 for demodulation into AF signals.
The FM detector circuit employs a quadrature detection
method (linear phase detection), which uses a ceramic dis-
criminator (X2) for phase delay to obtain a non-adjusting cir-
cuit. The detected signal from IC1 (pin 9) is applied to the AF
circuit.
3-1-5 AF AMPLIFIER CIRCUIT
The AF amplifier circuit amplifies the detected signals to
drive a speaker. The AF circuit includes an AF mute circuit
for the squelch.
AF signals from IC1 (pin 9) are applied to the de-emphasis
circuit (R92, C152). The de-emphasis circuit is an integrated
circuit with frequency characteristic of –6 dB/octave.
The integrated signals are applied to the active filters (Q21,
Q22). Q21 functions as a high-pass filter to suppress
unwanted lower noise signals and Q22 functions as a low-
pass filter to suppress higher noise signals.
The filtered signals are passed through the [VOLUME] con-
trol, and are then applied to the AF power amplifier (IC9, pin
1) via the analog switch (IC5, pins 4, 3). The output signal
from IC9 (pin 4) drives the internal (external) speaker.
Mixer
16
Limiter
amp.
2nd IF filter
450 kHz
PLL IC
IC3
X1
15.2 MHz
X2
(30.4 MHz)
RSSI
IC1 TA31136F
13
1st IF (30.85 MHz)
from Q3
"SQL" signal to the CPU pin 22
11
10
9
8
7
5
3
AF signal "DET"
R5
R22
C53
R26
C54
C42
R23
C50
R25
C51
Squelch level
adjustment pot
R1 (VR-B unit)
2
17
16
Active
filter
FI2
Noise
detector
FM
detector
2
• 2ND IF AND DEMODULATOR CIRCUITS