4 - 6
The detected signal output from the PLL IC (pin 2) is
converted into a DC voltage (lock voltage) at the loop filter
and then fed back to one of the VCO circuits (Q5521,
D5521, L5523).
The oscillated signal from the buffer amplifier (Q5601) is
also applied to the MAIN unit via the “M1LO” line as a 1st
LO signal after being amplified at LO (Q5602) and buffer
(Q5603) amplifiers or passed through the bandpass filter
(L5602–L5604, C5610–C5616).
4-3-3 2ND LO AND REFERENCE OSCILLATOR
CIRCUITS (PLL UNIT)
The reference oscillator (X5251) generates a 32.0 MHz
frequency for the DDS circuits as a system clock and
for the LO output. The oscillated signal is doubled at the
doubler circuit (Q5202) and the 64.0 MHz frequency is
picked up at the double tuned filter (L5203, L5204). The
64.0 MHz signal is applied to the RF circuit via the “M2LO”
line as a 2nd LO signal.
4-3-3 3RD LO CIRCUIT (PLL UNIT)
The DDS IC (IC5701) generates a 10-bit digital signal using
the 32 MHz system clock. The digital signal is converted
into an analog wave signal at the D/A converter (R5701–
R5720). The converted analog wave is passed through the
low-pass filter (L5781–L5783, C5781–C5785) and is then
applied to the MAIN unit as the 3rd LO signal (422.500
kHz) via the attenuator (R5781–R5783).
4-4 FRONT UNIT (RC-26)
4-4-1 LCD CIRCUIT (DISPLAY AND CONNECT
BOARDS)
The LCD (CONNECT board; DS8920) is controlled by the
LCD driver (CONNECT board; IC8940) via the drive signals
(CL1, RES, CS, RS, WR, RD, DB0–DB7) from the display
board. The LCD’s back light employs 5 LEDs (DS8300–
DS8304). The LEDs are controlled by dimmer (Q8300,
Q8303) and dimmer controller (IC8280) circuits.
4-4-2 MICROPHONE CIRCUIT (DISPLAY BOARD)
The AF signals from the microphone are amplified at the
AF amplifier (IC8280) via the “MIC” signal. The signals are
applied to the IC-F7000’s main unit through the J2501, pin
1 via the “FMOD” line.
4-4-3 KEY’S BACK LIGHTS CIRCUIT (DISPLAY
BOARD)
The key”s back lights compose of DS8305, DS8306,
DS8308, DS8309, DS8311–DS8314, and are controlled
by the dimmer (Q8301) and dimmer controller (IC8280)
circuits. The dimmer circuit is controlled by the FRONT
CPU.
4-4-4 RESET CIRCUIT (DISPLAY BOARD)
The reset IC (IC8202) resets the FRONT CPU (IC8201)
when IC-F7000 is power ON or OFF.
• PLL CIRCUIT
Phase
detector
Programmable
divider
Programmable
divider
Loop filter
Doubler
DDS
DDS
D/A
convertor
D/A
convertor
Buff
Loop filter
Buff
PLL IC (IC5401)
MAIN loop VCO
Q5601
Q5604
Q5602
Q5202
Q5302
Q5301, D5301
Q5351
Reference OSC. (32 MHz)
X5251; [USA], [CAN]
X5281; [OTH]
Reference loop VCO
IC5701
Q5603
Q5521,
D5521,
L5523
DDS IC
(IC5101)
LO
LO
AMP.
Buff
1st LO
(64 94 MHz)
2nd LO
(64 MHz)
3rd LO
(443 kHz)
Phase
detector
Programmable
divider
Programmable
divider
