4 - 5
4-5 PORT ALLOCATIONS
CPU (IC20)
20
21
22
24
25
30
31
32
38
40
43
44
47, 48
49
50
51
53
55
56
25
57
60
62
PTTO
PTTI
AFON
BUSY
POSW
MMUT
RMUT
NOIS
AFV
RSSI
CDEC
CENC
ECS2,
ECS1
ECK
ESI
ESO
BEEP
MCON
AMUT
NWC
HFSW
PA
TMUT
Outputs the PTT control signal.
Low : While transmitting
Input port for the PTT control signal
from PTTO port.
Input port for the AF amplifier ON sig-
nal from an optional unit.
Outputs busy signal for an optional
unit.
Input port for the power switch.
Low : While power switch is pushed
Input port for microphone audio mute
control signal from an optional unit.
Input port for receive audio mute con-
trol signal from an optional unit.
Input port for noise signals (pulse-
type) for noise squelch operation.
Input port for the volume control.
Input port for receiving signal strength
level detection.
Input port for CTCSS/DTCS decoding.
Output ports for CTCSS/DTCS sig-
nals.
Output ports for EEPROM select sig-
nals.
ECS1: For internal EEPROM (IC27)
ECS2: For optional EEPROM
Outputs clock signal for EEPROMs.
Input port for serial signal from
EEPROMs.
Outputs serial signal for EEPROMs.
Outputs beep audio signals.
Outputs mic. audio mute control signal
to the audio switch (IC25).
High : While DTMF signals are being
transmitted, etc.
Outputs the AF mute switch (Q6) con-
trol signal.
High : While squelched, etc.
Outputs N/W switch control signals.
High : While wide is selected
Outputs high-pass filter’s characteris-
tics select signal.
High : During CTCSS operation
Outputs mic. audio select signal to the
audio switch (IC25).
High : While “Public-address” func-
tion is ON
Outputs MT8V regulator circuit (Q38,
D27) control signal.
High : While transmit is muted.
64
65
66
67
68
69
72
73
75
76
77
78
79
80
82–89
93
99
DSTB
DDA
DCK
PSTB
PDA
PCK
UNLK
PLLT
VTX
VRX
PWON
PASP
SP
DIM
DTR1–
DTR4,
DTC4–
DTC1
HORN
SIFT
Outputs strobe signals for the level
controller. (IC5)
Outputs data signal for the level con-
troller (IC5).
Outputs clock signal for the level con-
troller (IC5).
Outputs strobe signals for the PLL IC
(IC12).
Outputs data signal for the PLL IC
(IC12).
Outputs clock signal for the PLL IC
(IC12).
Input port for the PLL unlock signal.
High : During unlock
Outputs PLL accelerator control signal.
High : While scanning, etc.
Outputs the T8V regulator circuit (Q38,
D28) control signal.
Low : While transmitting
Outputs the R8V regulator circuit
(Q36, D27) control signal.
Low : While receiving
Outputs the power control circuit (Q12)
control signal.
High : During power ON
Outputs “Public-address” mute signal.
High : While PA and Ext. SP func-
tions are not used
Outputs the mute switch (Q7) control
signal (incl. beep).
High : While squelched, etc.
Input port for an external LCD back-
light brightness control signal.
Low : LCD backlight is dimmed
Outputs DTMF audio signals.
Outputs high level control signal for the
pre-set time to the connected external
unit when matched 2- or 5-tone code is
received.
Outputs CPU clock shift signal.
Pin
Port
Description
number
name
Pin
Port
Description
number
name
