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4 - 6
Pin
number
5
7
11
12
13
14
Port
name
DETMITE
R5C
WXC
ANLC
EMBI
AFC
Description
Outputs detector mute signal to the
AM/FM select switch (IC2, pin 2).
Outputs receiver 5V control signal to
the RX controller (Q20).
Outputs AM/FM (WX ch) select signal
to the RX shift circuit (Q34, D25) and
AM/FM select switch (IC2, pin 5).
Outputs control sigal to the ANL switch
(Q21).
Outputs control signal to the external
microphone controller (Q25, Q26,
D23, D27).
Outputs control signal to the AF out
cotnroller (Q35, Q36) for the AF power
amplifier (IC6).
4-5-2 SHIFT RESISTOR (RF UNIT; IC5)
Pin
number
4
5
6
7
11
12
13
Port
name
VORON
PLAYC
RECC
LIGHTC
BLEDC
MMUTE
ALCC
Description
Outputs control signal to the VOR
controller (Q15).
Outputs playback control signal to the
voice rec/play IC (IC15, pin 23).
Outputs recording control signal to the
voice rec/play IC (IC15, pin 27).
Outputs LCD backlight control signal.
Outputs BUSY LED control signal.
Outputs control signal to the Mic mute
switch (Q12) for internal microphone.
Outputs control signal to the ALC con-
troller (Q11).
4-5-3 SHIFT RESISTOR (LOGIC UNIT; IC8)
4-5 PORT ALLOCATIONS
4-5-1 CPU (LOGIC UNIT; IC1)
Pin
number
1
2
3
4
5
6
7
8
9
10
11
12,
21
17
18
19
20
22
23
24
25
32
33
47
48
54
55
Port
name
VIN
VORD
RSSI
RFDETV
THRMC
SBATT
PDATA
PCK
PSTB
BEEP
VORS
DICK,
DIUD
LIGHT
BPCPI
CLOUT
CLIN
VORC
POWER
PTT
JACKDET
DCC
RESET
EDATA
UNLK
PCON
ECK
Description
Input port for the battely voltage
detection.
Input port for the VOR signal detec-
tion.
Input port for the receive signal level.
Input port for the power detection of
power amplifier (RF unit; Q2).
Input port for the transceiver’s internal
temperature.
Input port for the battely type detec-
tion.
Outputs data signals to the PLL IC (RF
unit; IC3).
Outputs clock signal to the PLL IC.
Outputs strobe signals to the PLL IC.
Outputs beep audio signals.
Input port for the 30 Hz phase signal.
Input port for [DIAL].
Input port for [LIGHT] switch.
Outputs the bias control signal for a
type of battery.
Outputs the cloning signal.
Input port for the cloning signal.
Input port for the VOR 30 Hz standard
signal.
Input port for [POWER] swtich.
Input port for the [PTT] swtich.
High: While [PTT] switch is pushed.
Input port for the external SP jack con-
nection detection.
High: While the external SP jack is
connected.
Input port for the external DC connec-
tion detection.
Input port for the CPU reset signal.
• Input port for the data signals from
the EEPROM (LOGIC unit; IC7).
• Outputs data signals to the EEP-
ROM IC.
Input port for the PLL unlock signal.
Low: PLL is unlocked.
Outputs control signal for the 5V regu-
lator.
Outputs clock signal to the EEPROM
IC (LOGIC unit; IC7).