3 - 7
3-4 CPU PORT ALLOCATIONS
Pin
No.
Line
Name
Description
I/O
3 VBUS
VBUS connection detect for USB HUB.
H=USB connection detected.
I
8
DAVOX
MIC signal detect.
H=Input detect.
I
9 CTFL
CW
TX
status.
I
11 RTKI
RTTY keying input.
H="Space" input.
I
12 UNLK
PLL (ADF4630) unlock detect.
L=Unlock detected.
I
14
VSQM
Squelch level input.
H=Squelch open.
I
16
RTDM
RTTY decode data from the DSP.
I
19
MHSK0
Handshake signal from the DSP.
I
23
FRES
Front CPU reset signal.
O
26 HIFOP1K
Optional IF filter (bandwidth=6 kHz)
installation detect.
L=Installed.
O
27 HIFOP2K
Optional IF filter (bandwidth=3 kHz)
installation detect.
L=Installed.
O
31 TRVI
Transverter input (from [ACC2]).
L=A transverter is connected.
I
33
UDTXD
Data output port for [USB] connector.
O
35 PWRS
Transceiver power ON/OFF control.
H=Power ON.
O
36 UPWS
USB HUB power control.
H=USB power ON.
O
37
H8_
CS6#
Dual-port SRAM chip select signal.
L=Selected.
O
38
H8_
CS7#
Expander chip select signal.
L=Selected.
O
42
PCK
PLL serial clock.
O
43
PDAT
PLL serial data.
O
44 PSL
PLL
strobe.
O
45
PST
PLL strobe output.
O
46 SKYS
Straight key/electronic keyer input. (A/D)
L=Key down.
I
47 EXRL
External SEND reray output.
H=Relay ON
O
48 ESTA
External tuner "START" signal output.
L=Tuning start.
O
49 EKEY
External tuner "KEY" signal input.
L=While tuning/tune NG.
I
51
MCK
Common serial clock.
O
52
MDAT
Common serial data.
O
53
TCON
External tuner conection detect.
I
54
CTXD
CI-V (UART) output.
O
55
CRXD/
CBSY
CI-V (UART) input/CI-V bus busy input.
L=Data "1" /Busy.
I
56
PCK/
CON0
DDS clock.
O
56 DSPCK
DSP
clock.
O
57 DSPR
DSP
data.
O
59
UDRXD
USB data input.
I
73–
80
H8_D8–
H8_D15
DSP address bus.
O
82
TND
QPSK (L) decode data.
I
Pin
No.
Line
Name
Description
I/O
83 NSQ
Noise
pulse.
I
84
PSENI
Microphone PTT input.
H=While transmitting.
I
84
H8_
WAIT#
Bus control "Wait" signal.
I
85 TRAS
SEND
signal.
O
87
H8_
LWR#
(Bus control) "L" write signal.
L=While writing.
O
88
H8_
HWR#
(Bus control) "H" write signal.
L=While writing.
O
89 H8_RD#
(Bus control) Read signal.
L=While reading.
O
90
H8_AS#
(Bus control) Adress strobe.
O
92
RES
CPU reset.
H=Reset.
O
94 SENI
PTT/ACC SEND signal.
H=While transmitting.
I
105 DSKY
DSP CW/RTTY keying signal.
L=Key down/space.
O
115
VOXL
VOX level input.
I
121
DX1
TX/RX DSP data.
I
124
THRI
Internal tuner through signal.
H=Tuner through.
I
125
BEEP
Beep audio.
O
126
STON
Side tone.
O
133 LTXD
Data output (UART) for the communication
with the front CPU.
O
134 LRXD
Data input (UART) for the communication
with the front CPU.
I
135
PWRK
[POWER] input. (Pull-up)
I
137
EDT
EEPRROM data.
I/O
138 ECK
EEPRROM
clock.
O
140 IKEY
Internal tuner "KEY" input (UART).
L=Tuner ON.
I
142
ISTA
Internal tuner "START" signal (UART).
O
• MAIN CPU (MAIN UNIT: IC1201)
• EXPANDER (MAIN UNIT: IC1161)
Pin
No.
Line
Name
Description
I/O
12
FORL
Forward wave detect voltage. (A/D)
I
1
REFL
Refl ected wave detect voltage. (A/D)
I
14
ALCL
ALC meter voltage input. (A/D)
I
5
IDL
Drive AMP current (ID) detect voltage. (A/D)
I
4
VDL
Drive AMP voltage (VD). (A/D)
I
15 THML
Temperature sensing voltage from the
thermal sensor on the PA-A UNIT. (A/D)
I