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preliminary 

preliminary 

iC-PVS

LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR

Rev A2, Page 42/51

status byte (STATUS) and an optional data byte (DATA)
is immediately returned on MISO.

The SPI status byte is defined in Table 54. The status

bits are updated with every register access only, except
Invalid Opcode, which indicates the status of the

last

opcode transmitted to the slave.

SPI STATUS

Bit

Name

7

Invalid opcode

6:3

Reserved

2

Data request failed

1

Reserved

0

Data valid

Table 54: SPI Status byte

The opcode Get Register Communication Status is use-

ful in conjunction with the opcodes Read Register - I2C
Slave Access (0x97) and Write Register - I2C Slave

Access (0xD2) and allows to check the status of the

rather slow I2C read / write transactions. The data byte

(DATA) is only defined if opcode Read Register - I2C

Slave Access (0x97) has been sent before. In that case
it contains the requested data byte.

An explanation of the individual status bits can be found

below:

Invalid Opcode

The opcode transmitted is not supported by iC-PVS.

Data request failed

Register read/write attempt failed. Possible causes
are an unsupported address, RPL active or trying to
read/write a non readable/writable address.

Data valid

Data read via opcode Read Register - I2C Slave Ac-
cess (0x97) is valid and can be used. Data written via
opcode Write Register - I2C Slave Access (0xD2) has
been written.

Multi-slave configurations with iC-PVS

The common SPI bus configuration for two iC-PVS

slaves is illustrated in Figure 28. Each slave is individu-
ally addressed by the SPI master via a dedicated NCS
line. Only one slave may be addressed at the same
time.

Figure 28: SPI bus configuration

Another possibility to connect multiple iC-PVS is by

setting up an SPI daisy chain as shown in Figure 29.

The MOSI of each iC-PVS is connected to the MISO of

the next device in chain. The MISO of each iC-PVS is
connected to the MOSI of the next device. As only a
single NCS line is used, individual slaves are selected
via the opcode Activate Slave In Chain.

Please refer to the opcode Activate Slave In Chain de-
scription below for further information on setting up a
SPI daisy chain with iC-PVS.

Figure 29: SPI daisy chain configuration

Summary of Contents for iC-PVS

Page 1: ...ery loss of magnet and RAM CRC monitoring APPLICATIONS Freely scalable hollow shaft absolute multiturn position sensors Freely scalable linear absolute position sensors Ferrous gear wheel or magnetic scale scanning Configurable magnetic sensing heads PACKAGES dra_qfn38 1_pack_2 2 4 1 38 pin QFN 5 mm x 7 mm RoHS compliant BLOCK DIAGRAM iC PVS Serial I O Interface Absolute Data Serial Interface Coun...

Page 2: ...ration from one of the I O interfaces An undervoltage reset zeroes internal reg isters Furthermore the pin PRE serves as a preset input high active Additional to EEPROM readout the I2 C interface can also be used for direct register communication via the I2 C protocol The period counter stage is designed for ultra low power applications and can be configured to support angular accelerations up to ...

Page 3: ...evolution Counter Length 26 SBL_ADI Synchronization Bit Length 26 PCR_ADI Period Counts per mech Revolution 26 ERR_ADI Transmission of Error Bit 27 WRN_ADI Transmission of Warning Bit 27 DIR_ADI Code Direction Inversion 27 ERR_PDR Error on Power Down Reset and Preset 27 OS_ADI Code Offset of Absolute Position 28 ENSOL Enable Sign Of Life Counter 28 CRCS_BISS and CRC16_BISS BiSS CRC 28 PERIOD COUNT...

Page 4: ...Get Register Communication Status 41 Multi slave configurations with iC PVS 42 Activate Slave In Chain 43 I2 C EEPROM INTERFACE 44 I2 C SLAVE INTERFACE 45 COMMANDS 46 REBOOT 47 RESET 47 SLEEP 47 STANDBY 47 SCLEAR 47 FORCE_REQ and UNFORCE_REQ 47 CHIP_ID 47 STATUS REGISTERS 48 Status Register Overview 48 STUP_ERR Startup Error 48 CFG_ERR Internal Configuration Error 48 CTR_ERR Internal Counter Error...

Page 5: ...n c 23 n c 24 n c 25 n c 26 n c 27 n c 28 n c 29 n c 30 n c 31 n c 32 NCOS Analog Output Negative Cosine 33 PCOS Analog Output Positive Cosine 34 NSIN Analog Output Negative Sine 35 PSIN Analog Output Positive Sine 36 VDD 3 15V to 5 5V Main Supply Voltage 37 VDDS 1 Switched Supply Voltage Output 38 VBAT2 Battery Supply Voltage Input typ 3 6 V BP3 Backside Paddle IC top marking P CODE product code ...

Page 6: ...er package vs center hall sensor array 3 65 5 65 0 22 0 40 0 50 BOTTOM 0 90 0 10 0 48 SIDE 4 90 3 65 5 65 6 90 R0 15 0 50 0 30 0 70 RECOMMENDED PCB FOOTPRINT dra_qfn38 5x7 1_pvs_z_pack_1 10 1 All dimensions given in mm Tolerances of form and position according to JEDEC MO 220 Tolerance of sensor pattern 0 10mm 1 with respect to center of backside pad ...

Page 7: ...0 mA G009 I Current in all other pins except VDD VBAT VDDS and GND 30 30 mA G010 Vd ESD Susceptibility at All Pins HBM 100 pF discharged through 1 5 kΩ all pins relative to GND 2 kV G011 Tj Chip Junction Temperature 40 150 C THERMAL DATA Operating conditions VDD 3 15 5 5 V VBAT 3 0 5 0 V GND 0 V Item Symbol Parameter Conditions Unit No Min Typ Max T01 Ta Operating Ambient Temperature Range QFN38 5...

Page 8: ...DDS ceramic capacitor placed as close as possible to the pin 1 1 µF 012 C VDD External Bypass Capacitor at Pin VDD ceramic capacitor placed as close as possible to the pin 1 1 µF 013 tstup VDD Startup Time Analog Signal Path after VDD Power Cycle Standby or Sleep ENAC 0 1 2 ms ENAC 1 3 6 ms Magnetic Signal Conditioning 101 hpac Sensor to Package Surface Distance QFN38 5x7 0 4 mm 102 Hmax Permissib...

Page 9: ...ted with IBIAS 5 0 6 0 7 0 MHz Supply Switch and Monitoring 401 Vpor Internal Power On Reset increasing voltage at VBAT V VDD Von 2 70 2 80 2 95 V 402 Vpdr Internal Power Down Reset decreasing voltage at VBAT V VDD Von 1 25 1 80 2 35 V BAT_MON 00 battery monitoring disabled 403 Vbout Battery Monitoring Brown Out Threshold Voltage BAT_MON 00 battery monitoring enabled 2 65 2 75 2 90 V 405 Von Switc...

Page 10: ...k CLK Permissible Clock Frequency at CLK SPI protocol 4 MHz SSI protocol 4 MHz BiSS C protocol 10 MHz 802 Vt hi Threshold Voltage hi 1 7 2 V 803 Vt lo Threshold Voltage lo 0 8 1 4 V 804 Vt hys Hysteresis Vt hys Vt hi Vt lo 100 250 500 mV 805 Ipu Pull Up Current at CLK SI NCS V 0 V VDDS 1 V 75 30 3 µA 806 Ipd Pull Down Current at GPIOx V 0 V 1 V 3 30 75 µA Preset Input PRE 901 Tpulse PRE Permissibl...

Page 11: ...tion 125 tout ns I006 tP3 Propagation Delay 10 50 ns I007 tout Slave Timeout see Elec Char A01 BiSS C protocol DIOMODE 0x0 I008 tframe Permissible Frame Duration indefinite I009 tC Permissible Clock Period refer to Elec Char 801 for clock frequency 100 ns I010 tL1 Clock Signal Hi Level Duration 50 tout ns I011 tL2 Clock Signal Lo Level Duration 50 tout ns I012 tbusy Processing Time 2 tC I013 tP3 P...

Page 12: ...2 Propagation Delay MISO high impedance after NCS lo hi 100 ns I106 tH1 Hold Time NCS lo after SCK lo hi valid for SPI mode 3 100 ns I107 tS2 Setup Time MOSI stable before SCK lo hi 100 ns I108 tH2 Hold Time MOSI stable after SCK lo hi 20 ns I109 tP3 Propagation Delay MISO stable after MOSI change mode repeating MOSI on MISO 100 ns I110 tP4 Propagation Delay MISO stable after SCK hi lo mode sendin...

Page 13: ...t CRC Checksum for BiSS NTOA_BiSS Fixed or Adaptive BiSS Timeout Supply Switch and Monitoring Page 29 BAT_THR Battery Monitor Thresholds BAT_MON Battery Monitor Enable MON_FRQ Battery Monitor Sampling Frequency VON5 Set Typical Supply Voltage Magnetic Signal Conditioning Page 31 POLEWID Pole Size of Magnetic Scale DCCOMP High Magnetic Field Strength Compen sation A_MAX Maximum Angle Acceleration M...

Page 14: ...SS CRCS_BISS 5 0 Supply Switch and Monitoring B0 0x08 MON_FRQ 2 0 BAT_MON 1 0 BAT_THR 2 0 Magnetic Signal Conditioning B0 0x09 0 0 DCCOMP 0 POLEWID 3 0 B0 0x0A NOMAG 1 0 MAGTHR 1 0 VON5 A_MAX 2 0 B0 0x0B OSS 7 0 B0 0x0C OSC 7 0 B0 0x0D 0 0 ENOG OSD LOWPOW 1 0 GCOARSE 1 0 Frequency and Bias Current Adjustment B0 0x0E 0 0 0 IBIAS 4 0 B0 0x0F 0 0 0 0 0 0 0 0 Analog Output B0 0x10 GAINF 10 3 B0 0x11 G...

Page 15: ... 0 B1 0x07 SERIAL_0 7 0 BiSS ID B1 0x08 DEV_ID_5 7 0 B1 0x09 DEV_ID_4 7 0 B1 0x0A DEV_ID_3 7 0 B1 0x0B DEV_ID_2 7 0 B1 0x0C DEV_ID_1 7 0 B1 0x0D DEV_ID_0 7 0 B1 0x0E MFG_ID_1 7 0 B1 0x0F MFG_ID_0 7 0 Bank 7 BSEL 0x07 Position Preload Addresses Mirrored from B0 0x1A 0x1F Usable for end user position preloading if BANK 0 is write protected Position Preload B7 0x18 PCTR_PREL 7 0 B7 0x19 PCTR_PREL 7 0...

Page 16: ...lute Data read only 0x50 0 0 IPO 5 0 0x51 PC 7 0 Period Counter 0x52 PC 15 8 Period Counter 0x53 RC 7 0 Revolution Counter RC Revolution Counter 0x57 RC 39 32 Revolution Counter Actual Gain Factor read only 0x5C AGAINS 10 3 0x5D 0 0 0 0 0 AGAINS 2 0 0x5E AGAINC 10 3 0x5F 0 0 0 0 0 AGAINC 2 0 Status Register 0x6C STATUS 7 0 0x6C ANA_STUP NOMAG_L AMPL_ERR BAT_ERR POS_ERR CTR_ERR CFG_ERR STUP_ERR 0x6...

Page 17: ... in Figure 9 From the periodic magnetic field delivered by the tar get the hall sensor array generates internal sensor signals which are then further processed and passed to the analog output as shown in Figure 10 These analogue sensor signals can then be used as an input to a downstream interpolator device for high resolu tion sine to digital conversion and signal processing Additionally a fast a...

Page 18: ... as 360 m consists of multiple magnetic periods On every magnetic pole pair one electrical sine period is gener ated on the analog output referred to as 360 e Figure 8 shows an example code disc with 32 magnetic pole pairs Here 360 e correspond to 11 25 m The wheel has to turn 11520 e for one full mechanical rotation of 360 m The absolute FlexCount feature of iC PVS can be utilized to interpret th...

Page 19: ...This puts all circuitry to a defined init state Note The power on reset voltage threshold is no sufficient working condition The device will only be bootable and utilizable if VDD is risen above Von see Figure 12 If battery backup is not used it is necessary to tie pins VBAT and VDD together Pin VBAT must not be left open The permissible voltage range of VBAT is noted in Elec Char 004 As a second ...

Page 20: ...R 1 iC PVS can be brought into ACTIVE_ST if STUP_ERR is cleared by sending a SCLR command In that case iC PVS loads a default configuration which means that that all configuration parameters are set to their specified reset value 2 The EEPROM does not contain a valid configura tion and the CRC check fails In that case iC PVS will stay in BOOT_ST indicated by STUP_ERR 1 Depending on the invalid dat...

Page 21: ...backup battery is connected High speed capable Yes OK 50 mA 0 mA BATTERY Off Backup operation using VBAT supply current consumption depends on rotational speed and parameter A_MAX High speed capable No OK 0 mA 10 µA NOMAG On Low magnetic field amplitude detected Low speed Yes Error 3 mA 0 mA NOMAG Off Low magnetic field amplitude detected current consumption defined by parameter A_MAX Low speed No...

Page 22: ...ice requirements EEPROM Device Requirements Supply Voltage 2 5 V to 5 5 V Power On Threshold 2 9 V due to Elec Char 405 Addressing 11 bit address max Device Address 0x50 1010 000 w o R W bit Page Buffer Not required Size Min 1 Kbit 128x8 bit type 24C01 for configuration data Size Max 16 Kbit 8x 256x8 bit type 24C16 Size limited due to 11 bit slave addressing Table 5 EEPROM Device Requirements EEPR...

Page 23: ...s can be individually protected against write or read ac cess The register protection level RPL can be set by selecting the bank using BSEL and then executing the command RPL_SET_RO read only or RPL_SET_NA no access no read or write This setting must then be stored in the EEPROM To check the current protec tion level of the selected bank execute the command RPL_GET In general access privileges can...

Page 24: ...5 0 all 0x051 0x051 Period Counter 0x052 0x052 all 0x053 0x053 Multiturn Counter 0x057 0x057 all 0x06C rw 0x06C Status Register 0x06E 0x06E all 0x076 ro 0x076 0x077 rw 0x077 all 0x078 ro 0x028 BiSS ID 0x07F 0x02F 0x01 0x001 0x030 unused 0x01 0x002 0x03F 0x003 0x01 0x004 0x007 0x01 0x008 0x00F 0x07 0x018 0x01F EEPROM_ADDR BSEL 0x20 0x40 ADDR 0x20 none na 0x21 0x000 0x040 0x23 0x03F 0x0FF 0x24 0x000...

Page 25: ...7 lists further options DIOMODE 2 0 Addr 0x00 bit 2 0 reset 0x0 Code NCS CLK SI SO Function 0x0 MA SLI SLO BiSS 0x1 MA SLO ExtSSI w CRC 0x2 MA SLO ExtSSI w o CRC 0x3 NCS SCLK MOSI MISO SPI 0x4 NCS SCLK MOSI MISO SPI tristate 0x5 SYNC5 SYNC4 SYNC3 Absolute Sync 0x6 Z B A Incremental Note When in DIOMODE 0x2 the data format can be configured to match the standard SSI protocol Table 7 Serial Interfac...

Page 26: ...ated by the iC PVS ADC stage with a maximum resolution of 64 steps per electrical period Depending on the later usage of this fine position information the wording synchronization information SYNC and interpolated position IPO are used equally throughout this datasheet If iC PVS is used in conjunction with a high resolution singleturn encoder or interpolator this data is used to synchronize the ab...

Page 27: ...its after rev data Table 13 Enable Period Counter Output ERR_ADI Transmission of Error Bit Parameter WRN_ADI enables the error bit transmission according to Table Table 14 The error bit nERR is an active low status bit When any bit in the STATUS 7 0 register at address 0x6C is set an error is generated by transmitting a 0 Otherwise a 1 is transmitted Refer to chapter Status Registers on page 48 fo...

Page 28: ... the BiSS or SPI interface If the sign of life counter is enabled ENSOL 1 a 6 bit count value 1 63 is transmitted as specified in Table 9 The count value is incremented after each absolute data frame transmitted If the sign of life counter is dis abled ENSOL 0 no additional bits are transmitted ENSOL Addr 0x5 bit 7 reset 0 Code Value 0 No sign of life counter is transmitted 1 A 6bit sign of life c...

Page 29: ...Preload Value SUPPLY SWITCH AND MONITORING To retain and track the absolute position on main power shutdown iC PVS monitors VDD and switches in be tween VDD and battery supply on pin VBAT automat ically The switching points are defined in Elec Char 406 and 405 If the main supply voltage on VDD drops below the Voff threshold the internal circuitry is pow ered by VBAT instead of VDD To save power th...

Page 30: ... Monitor Sampling Frequency To save power the battery monitoring is not continu ously enabled The sampling frequency can be con figured using parameter MON_FRQ according to table 26 MON_FRQ 2 0 Addr 0x08 bit 7 5 reset 000 Code Sampling Frequency Sampling Period I VBAT typical 0x0 0 5 Hz 2000 ms 5 nA 0x1 2 Hz 500 ms 10 nA 0x2 8 Hz 125 ms 39 nA 0x3 32 Hz 32 ms 156 nA 0x4 125 Hz 8 ms 625 nA 0x5 500 H...

Page 31: ...All common magnetic disc or wheel applications without backbias magnet 0 Backbias magnet Field range 180 180 kA m 1 Backbias magnet Field range 380 380 kA m Table 29 High Magnetic Field Strength Compensation LOWPOW Low Power Mode When iC PVS is powered via VDD the magnetic signal acquisition can run in four different power modes In de fault mode the maximum permissible input frequency is equal to ...

Page 32: ...vided for each channel With Parameter OSD the value of the offset voltage correction can be doubled Table 34 The offset compensation is inactive by default It is activated with parameter ENOG Table 35 OSD Double Offset Factor OSD Addr 0x0D bit 4 reset 0 Code Enable Offset Generation Block 0 Offset values according to Table 33 1 All values in Table 33 doubled Table 34 Double Offset Factor ENOG Enab...

Page 33: ...otal actual gain can be obtained by multiplying GCOARSE by AGAINS or AGAINC AGAINS 10 3 Addr 0x5C bit 7 0 read only AGAINS 2 0 Addr 0x5D bit 2 0 read only Code Actual Fine Gain Factor Sine Channel 0x000 1 0000 0x001 1 0015 0x002 1 0029 exp ln 20 2048 GAIN 0x7FF 19 9708 Table 40 Actual Fine Gain Factor Sine Channel AGAINC 10 3 Addr 0x5E bit 7 0 read only AGAINC 2 0 Addr 0x5F bit 2 0 read only Code ...

Page 34: ...cal values in case of enduring move ment at a certain angular velocity during battery supply A_MAX 2 0 Addr 0x0A bit 2 0 reset 000 Code αmax e s2 αmax rade s2 typ Iavg µA max Iavg µA 0x0 160 106 2700 103 80 120 0x1 40 106 700 103 40 60 0x2 10 106 170 103 20 30 0x3 2 5 106 42 103 10 15 0x4 625 103 10 103 5 10 0x5 160 103 2 5 103 3 7 0x6 40 103 0 65 103 2 5 6 0x7 10 103 0 15 103 2 5 Note The values ...

Page 35: ...t should be calibrated so that the fre quency of the oscillator is close to 34 kHz see Elec Char No 301 The clock frequency is observable at output pin GPIO0 in the clock calibration mode GPI OMODE 0x0A See Table 8 for reference Calibrating the oscillator frequency is not absolutely necessary to ensure iC PVS operation however it is recommended to conduct the calibration If left uncal ibrated main...

Page 36: ...istance If the actual movement of the motor causes faster AB signals than the MTD the AB edges transition dis tance will be limited to MTD If AB signals are continu ously limited by MTD the internal AB position increas ingly differs from the actual absolute position If the difference becomes too large the AB calculation will no longer work correctly and incorrect AB signals will be output e g with...

Page 37: ...ut 1 5 TBISS 1 5 TBISS 3 0 TSAMPLE Table 50 Adaptive timeout calculations For more information on the BiSS adaptive time out refer to BiSS application note AN23 at www biss interface com NTOA_BISS Addr 0x07 bit 7 reset 0 Code Value 0 Adaptive BiSS timeout 1 Fixed BiSS timeout Table 51 Fixed or Adaptive BiSS Timeout Control Communication The Control Communication uses the CDM and CDS bits of severa...

Page 38: ...values are transmitted MSB first For Extended SSI the iC PVS can provide a fixed or adaptive timeout depending on the setting of parameter NTOA_BISS shared configuration parameter for BiSS and Extended SSI The use of an adaptive timeout in SSI mode is not recommended Therefore NTOA_BISS should be set to 1 The SSI interface can also operate in external ring mode by connecting SLO of the last slave ...

Page 39: ...ristate high Z and clock signals on SCLK are ignored This allows connecting multiple SPI slaves to a single SPI master Refer to section Multi Slave configuration with iC PVS on page 42 for more information Each SPI transaction starts with one of the opcodes listed in 53 A SPI transmission including SCLK lines for mode 0 and 3 is illustrated in figure 19 OPCODE Code Description 0x81 Read Registers ...

Page 40: ...e first register to be written and the data With each data byte appended the address of the reg ister to be written is incremented by one ADR 1 If successfully received the same data stream is trans mitted on MISO by iC PVS This procedure may be continued for any number of consecutive registers as long as clock is sent and the slave stays active NCS low Read Position Opcode Position Read 0xA6 is u...

Page 41: ... will take additional time until completed Opcode Get Register Communication Status 0xAD is used to poll for the current I2C communication status and requested data Once the Data Valid bit is set the returned data can be used No further register commu nication is allowed while the transaction is active Write Register I2C Slave Access The opcode Write Register I2C Slave Access 0xD2 writes data to t...

Page 42: ...de transmitted is not supported by iC PVS Data request failed Register read write attempt failed Possible causes are an unsupported address RPL active or trying to read write a non readable writable address Data valid Data read via opcode Read Register I2C Slave Ac cess 0x97 is valid and can be used Data written via opcode Write Register I2C Slave Access 0xD2 has been written Multi slave configura...

Page 43: ...o MISO of the SPI master RACTIVE default 1 Code Description 0 Register communication deactivated 1 Register communication activated Table 55 RACTIVE RA PACTIVE default 1 Code Description 0 Sensor data channel deactivated 1 Sensor data channel activated Table 56 PACTIVE PA iC PVS 1 MOSI MISO Master MOSI MISO iC PVS 0 MOSI MISO PA1 RA1 PA0 RA0 Figure 31 SPI slaves after sending the Activate Slave In...

Page 44: ...th a combined write read command cycle as shown in Figure 33 The expected slave address is 0xA0 or 0b 1010 000 which is the standard I2 C EEPROM address Notes If several devices share one common EEPROM e g iC PVS used with an interpolator the default configuration area of iC PVS may not be usable addresses 0x00 to 0x1F Therefore the iC PVS is capable to boot from different addresses The EEPROM is ...

Page 45: ...e I2 C communication protocol described in Figure 33 may be used for read and write register access The position data can be read from direct access register 0x50 up to 0x57 Note For a consistent position information it is neces sary to stop the register updating before read out The commands FORCE_REQ and UNFORCE_REG must be used to freeze the data during multiple read cycles If the register 0x50 ...

Page 46: ...L4 Write current configuration to EEPROM Area 4 starting at address 0xA0 0x4F CONF_READ_SENSOR Read sensor configuration from internal RAM ROM e g after POLEWID has changed Group 8 Preset 0x81 ABS_PRESET Absolute stage preset to preload positions stored in RAM period CTR and revolution CTR 0x84 MT_CLEAR Multiturn counter clear to position 0 Group 9 GPIO 0x90 0x92 GPIO0 1_SET0 Set general purpose p...

Page 47: ...e If RESET is held active via GPIO1 in command mode the power consumption is reduced to a minimum All position tracking also the absolute stage is halted in that case SLEEP The SLEEP command stops all position sensing during battery mode and VDD mode Power consumption is reduced to a minimum but the serial interfaces are ac tive during VDD supply This is for example useful for the storage of encod...

Page 48: ...l RAM had an unexpected level flip of one or more bits visible as wrong CRC checksum Position is invalid Reboot iC PVS POS_ERR Position Error The position encoding observed an unexpected posi tion jump caused e g by excessive speed or excessive acceleration of the magnetic target Alternatively this error bit is set on weak disturbed magnetic signals or complete loss of magnet Position is invalid O...

Page 49: ...tatus bit is cleared as soon as the magnetic signal amplitude is within a valid range again AC_MAX Signal Amplitude High Always set in combination with AMPL_ERR Indicates that the magnetic signal amplitude is too high The status bit is cleared as soon as the magnetic signal amplitude is within a valid range again MAG_ERR Magnet Error The status bit is set if the NoMag detection is active and a mag...

Page 50: ...1 Parameter OSS OSC OSD Configuration bits are inverted 2 Parameter POLEWID 0x7 Parameter setting POLEWID 0x7 is not functional Do not use Table 62 Notes on chip functions regarding iC PVS chip release Y iC PVS X No Function parameter code Description and application notes 1 Parameter POLEWID 0x7 Parameter setting POLEWID 0x7 is not functional Do not use Table 63 Notes on chip functions regarding ...

Page 51: ...n case of only minor impairment of usability No representations or warranties either expressed or implied of merchantability fitness for a particular purpose or of any other nature are made hereunder with respect to information specification resp Documents or the products to which information refers and no guarantee with respect to compliance to the intended use is given In particular this also ap...

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