iC-Haus iC-PVS, Manual, Page: 41 / 51

preliminary preliminary
iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
Rev A2, Page 41/51
!
Commands do require processing time until
completed. Successful completion can be de-
tected by polling the CMD register. Refer to
chapter COMMAND REGISTER on page 46
for details.
Read Status Register
Opcode Read Status Register (0x9C) directly reads the
device status registers at address 0x6C - 0x6E.
Addr. 0x6C
OP
8 cycles
SCLK
MOSI
MISO
NCS
REQ
OP 0x00 STATUS (7:0)
Addr. 0x6D
STATUS (15:8)
Addr. 0x6E
STATUS (23:16)
Figure 24: Read Status Register
The SPI master transmits the Read Status Register op-
code (0x9C) on MOSI. The slave immediately outputs
the opcode on MISO followed by a delay byte 0x00 and
3 bytes containing the status register contents 0x6C to
0x6E. Refer to chapter Status Registers on page 48 for
details.
Read Register - I2C Slave Access
The opcode Read Register - I2C Slave Access (0x97)
reads data from the register at the specified address on
a byte by byte basis. It needs to be used for the access
of an external I2C slave (e.g. EEPROM).
ADR
8 cycles
SCLK
MOSI
MISO
NCS
OP
OP ADR STATUS OP
OP
DATA
+
1 2
Figure 25: Register Read (Single)
The SPI master transmits the opcode Read Register
- I2C Slave Access (0x97) followed by the address of
the register to read on MOSI. The slave immediately
outputs the opcode and address on MISO.
After the opcode has been received, the initiated I2C
communication will take additional time until completed.
Opcode Get Register Communication Status (0xAD) is
used to poll for the current I2C communication status
and requested data. Once the Data Valid bit is set, the
returned data can be used. No further register commu-
nication is allowed while the transaction is active.
Write Register - I2C Slave Access
The opcode Write Register - I2C Slave Access (0xD2)
writes data to the register at the specified address on a
byte by byte basis. It needs to be used for the access
of an external I2C slave (e.g. EEPROM).
ADR
8 cycles
SCLK
MOSI
MISO
NCS
OP
OP
DATA
ADR DATA STATUS OP
OP
+
1 2
Figure 26: Register Write (Single)
The SPI master transmits the opcode Write Register -
I2C Slave Access (0xD2) followed by the address of
the register and the data byte to be written on MOSI.
The slave immediately outputs the opcode, address
and data byte on MISO.
After the opcode has been received, the initiated I2C
communication will take additional time until completed.
Opcode Get Register Communication Status (0xAD) is
used to poll for the current I2C communication status.
The transaction is complete once the Data Valid bit is
set. No further register communication is allowed while
the transaction is active.
Get Register Communication Status
Opcode Get Register Communication Status (0xAD)
returns the SPI status byte and an optional data byte.
The status byte indicates the status of the last register
communication transaction.
STATUS
8 cycles
SCLK
MOSI
MISO
NCS
OP
OP
DATA
Figure 27: Register Status/Data
As shown in Figure 27 only the opcode (OP) has to be
sent on MOSI. The opcode (OP) followed by the SPI