Chapter 2. System-Board Features
PCI Bus
The fully synchronous 33 MHz PCI bus originates in the chip set. Features of the PCI bus are:
Integrated arbiter with multi-transaction PCI arbitration acceleration hooks for high performance
graphics
Built-in PCI bus arbiter with support for up to five masters
Microprocessor-to-PCI memory write posting with 5-Dword-deep buffers
Converts back-to-back sequential microprocessor-to-PCI memory write to PCI burst write
PCI-to-DRAM posting 18 Dwords
PCI-to-DRAM up to 100+ MB/sec bandwidth
Multitransaction timer to support multiple short PCI transactions within one PCI ARB cycle
PCI 2.1 compliant
Delayed transaction
PCI parity checking and generation support
Bus Master IDE Interface
The system board incorporates a PCI-to-IDE interface that complies with the
AT Attachment Interface with
Extensions. The subsystem that controls direct access storage devices (DASD) is integrated with the IDE
interface.
The chip set functions as a
bus master for the IDE interface. The chip set is PCI 2.1 compliant; it
connects directly to the PCI bus and is designed to allow concurrent operations on the PCI bus and IDE
bus. The chip set is capable of supporting PIO mode 0–4 devices and IDE DMA mode 0–2 devices, ultra
33 transfers up to 33 Mbytes/sec.
The IDE devices receive their power through a four-position power cable cont5, +12, and ground
voltage. When adding devices to the IDE interface, one device is designated as the master device and
another is designated as the slave or subordinate device. These designations are determined by switches
or jumpers on each device. There are two IDE ports, one designated 'Primary' and the other 'Secondary',
allowing for up to four devices to be attached.
For the IDE interface, no resource assignments are given in the system memory or the direct memory
access (DMA) channels. For information on the resource assignments, see “Input/Output Address Map”
on page 41 and Figure 48 on page 45 (for IRQ assignments).
Two connectors are provided on the riser for the IDE interface. For information on the connector pin
assignments, see “IDE Connectors” on page 31.
PCI-to-ISA Bridge
On the system board, the chip set provides the interface between the peripheral component interface
(PCI) and industry standard architecture (ISA) buses. The chip set is used to convert PCI bus cycles to
ISA bus cycles; the chip set also includes all the subsystems of the ISA bus, including two cascaded
interrupt controllers, two DMA controllers with four 8-bit and three 16-bit channels, three counters
equivalent to a programmable interval timer, and power management. The PCI bus operates at 33 MHz
Figure 1 (Page 2 of 2). System Memory Configuration
Total Memory (MB)
MEM 0
MEM 1
128
128
0
256
128
128
Chapter 2. System-Board Features
5
