Appendix A. Connector Pin Assignments
IDE Connectors
1
2
40
39
Figure 32 (Page 3 of 3). System Memory Connector Pin Assignments
Pin
x64 Non-Parity
x72 ECC
Pin
x64 Non-Parity
x72 ECC
80
NC
NC
164
NC
NC
81
NC
NC
165
SA0
SA0
82
SDA
SDA
166
SA1
SA1
83
SCL
SCL
167
SA2
SA2
84
VCC
VCC
168
VCC
VCC
Figure 33. IDE Connector Pin Assignments
Pin
Signal
I/O
Pin
Signal
I/O
1
NC
O
21
NC
NA
2
Ground
NA
22
Ground
NA
3
Data bus bit 7
I/O
23
I/O write
O
4
Data bus bit 8
I/O
24
Ground
NA
5
Data bus bit 6
I/O
25
I/O read
O
6
Data bus bit 9
I/O
26
Ground
NA
7
Data bus bit 5
I/O
27
I/O channel ready
I
8
Data bus bit 10
I/O
28
ALE
O
9
Data bus bit 4
I/O
29
NC
NA
10
Data bus bit 11
I/O
30
Ground
NA
11
Data bus bit 3
I/O
31
IRQ
I
12
Data bus bit 12
I/O
32
CS16#
I
13
Data bus bit 2
I/O
33
SA1
O
14
Data bus bit 13
I/O
34
PDIAG#
I
15
Data bus bit 1
I/O
35
SA0
O
16
Data bus bit 14
I/O
36
SA2
O
17
Data bus bit 0
I/O
37
CS0#
O
18
Data bus bit 15
I/O
38
CS1
O
19
Ground
NA
39
Active#
I
20
Key (Reserved)
NA
40
Ground
NA
Appendix A. Connector Pin Assignments
31