IBM 6400 Series, Maintenance Information Manual

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Chapter 5
The Power On Sequence
The Power On Sequence
This section describes the normal sequence of events from the time the
power switch is set to 1 until READY (or NOT READY, if so configured by the
user) appears on the LCD.
Use this sequence as a reference baseline to help you isolate problems that
occur before the printer completes its boot and initialization routines.
The power on sequence consists of two sets of routines:
1. CMX controller board handshake sequences (DC hardware initialization)
2. DC software initialization and power up
The routines are listed below, in order of occurrence.
CMX Controller Board Handshake Sequences
The first power-up routines are the handshaking sequences which sample
and test the condition of the CMX controller board. The sequences occur as
follows:
•
Processor Alive — The green LED marked CR1 on the CMX controller
board is turned on to indicate that the processor received a valid reset
vector and the first instructions to the processor are correct. This LED is
used to report all DC errors and states.
•
Test VX Data Bus — A walking zero and one test verifies that all 32 data
lines from the VX bus to the processor are connected. If a bad line is
detected, a 4-1-1-XX blink code is sent to the LED on the CMX controller,
where XX is the data line plus 1. (For example, a bad data line 8 would
blink as 4-1-1-9.)
•
Initialize VX ASIC — The boot code detects the processor type and sets
up the internal registers of the VX ASIC.
•
Initialize Debug Serial Port — The boot code checks the validity of the
debug serial parameters in NVRAM; if they are valid, it sets the baud rate,
data type, and which messages should be sent out the debug port. If the
values in NVRAM are not valid, boot code initializes NVRAM to 9600
baud, 8 data bits, one stop, bit, no parity bit, and standard messages.
•
Turn On Instruction Cache — The instruction cache is turned on to help
speed up memory tests and the entire boot process.
•
Enable DRAM Controller — A DRAM controller is built into the VX ASIC.
DRAM must be refreshed a few times to operate correctly. To speed the
boot process, the refresh rate is temporarily increased. The message
“TESTING HARDWARE PLEASE WAIT” is sent to the LCD, during which
time the refreshes run and finish. At this point, the fans start. After
sending the message, the refresh rate is set to the proper rate and DRAM
is ready to be tested.
•
Test I/O Clock — The VX ASIC has two clocks for internal timing, a
processor clock and an I/O clock. The processor clock cannot be checked
because the processor will not run without it, but the I/O clock can be
checked. The I/O clock is used for sending data to the operator panel and
to get the time for DRAM refreshes. If the boot code detects a problem