HYT TC-700P, Service Manual

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TC-700P Service Manual
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Figure 2 Diagram of PLL Circuit
(1) PLL Circuit
The PLL circuit adopts the second harmonic. The step frequencies available for the circuit are 2.5KHz,
5.0KHz or 6.25KHz. In U101, the 16.8MHz reference oscillator signal is divided into 2.5KHZ, 5.0KHz or
6.25KHz reference frequencies via a counter. The signal from the VCO goes through the buffer amplifier
Q107, and goes to U101, where it is divided by a frequency divider. Then the signal is compared with the
2.5KHz/5.0KHz/6.25KHz reference signal in a phase detector U101. After comparison, the signal goes
through a low-pass filter, and a DC level is generated. This level controls the VCO so as to control its
oscillation frequency.
(2) VCO
The operating frequency is generated via Q103 in TX mode and via Q101 in RX mode. The frequency
generates a control voltage via the phase detector to control the varactors (D105, D106, and D107 in TX
mode; D101, D102, D103 and D104 in RX mode) to make the oscillation frequency consistent with the
preset frequency of MCU. In RX mode, T/R is set to high level. In TX mode, T/R is set to low level. The
output from Q103 and Q101 is amplified by Q106 and then sent to the buffer amplifier.
(3) Unlock Detector
If the MUXOUT pin of U101 is at low level, unlock status occurs. If the microprocessor detects such
situation, TX operation is prohibited.
4. RX Circuit
The RX circuit utilizes double conversion superheterodyne techniques. The first IF is 44.85MHz and the
second IF is 455KHz. The first LO signal is supplied by the PLL & VCO circuit, and the second LO signal
is generated by the 44.395MHz crystal.