GMS81508/16
39
Interrupt Request Flag Register ( IRQH, IRQL)
Whenever interrupt request is generated, the interrupt request flag is set. The request flag
maintains '1" until interrupt is accepted. The accepted interrupt request flag is automatically cleared
by interrupt process cycle. Interrupt Request Flag Register ( IRQH, IRQL) is Read/ Write Register.
So, it is possible to be checked and changed by program.
2.12.3. Interrupt Priority
When two or more interrupts requests are generated at the same sampling point, the interrupt
having the higher priority is accepted. The interrupt priority is determined by H/W. however,
multiple priority processing through software is possible by using interrupt control flags(IENH, IENL,
I-flag) and interrupt mode register(IMOD).
Interrupt Masking Flag
0 : Interrupt Disable
1 : Interrupt Enable
<00F6
H
>
IENH
7
INT0E
6
INT1E
5
INT2E
4
INT3E
3
T0E
2
T1E
1
T2E
0
T3E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
<00F4
H
>
IENL
7
AE
6
WDTE
5
BITE
4
SE
3
-
2
-
1
-
0
-
R/W
R/W
R/W
R/W
-
-
-
-
Interrupt Request Flag
0 : Disable
1 : Enable
<00F7
H
>
IRQH
7
INT0R
6
INT1R
5
INT2R
4
INT3R
3
T0R
2
T1R
1
T2R
0
T3R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
<00F5
H
>
IRQL
7
AR
6
WDTR
5
BITR
4
SR
3
-
2
-
1
-
0
-
R/W
R/W
R/W
R/W
-
-
-
-