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Hynix Semiconductor GMS81508A User Manual Download Page 36

GMS81508/16

31

2.9.1.  Data Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 SIOM) to 

”

1

”

.    After one cycle of SCK,

SIOST is cleared automatically to 

“

0

”

. The serial output data from 8-bit shift register is output at

falling edge of Sclk. and input data is latched at rising edge of Sclk. When transmission clock is
counted 8 times, serial I/O counter is cleared as 

“

0

”

.    Transmission clock is halted in 

“

H

”

 state

and serial I/O interrupt (IFSIO) occurred.

Timing Diagram of Serial I/O

2.9.2.  The Serial I/O operation by Srdy pin

 

transmission clock = external clock

The Srdy pin becomes "L" by SIOST = "1". This signal tells to the external system that this device
is ready for serial transmission. The external system detects the "L" signal and starts transmission.
The Srdy pin becomes "H" at the first rising edge of transmission clock.

 

transmission clock = internal clock

The I/O of Srdy pin is input mode. When the external system is ready to for serial transmission, the
"L" level is inputted at this pin. At this time this device starts serial transmission.

SIOST

Srdy(Output)

SIOST

Srdy(Input)

D7

D6

D5

D1

D4

D3

D2

D0

D7

D6

D5

D1

D4

D3

D2

D0

Input Clock

Sclk

Latch

Output

IFSIO

Sin

Sout

SIOST

Summary of Contents for GMS81508A

Page 1: ...2 1 Nov 1998 Operating Temperature 10 75 C is extended to 20 85 C Add the unused port guidance on page 55 Correct errata for opcode of EOR dp X EOR dp Y EOR X in Instruction Set Add the OTP device pro...

Page 2: ...ic Interval Timer 18 2 5 WATCH DOG TIMER 19 2 5 1 Control of Watch Dog Timer 19 2 5 2 The output of WDT signal 20 2 6 TIMER 21 2 6 1 Control of Timer 23 2 6 2 Interval Timer 24 2 6 3 Event Counter 24...

Page 3: ...3 R2 PORT 50 3 4 R3 PORT 51 3 5 R4 PORT 52 3 6 R5 PORT 53 3 7 R6 PORT 54 3 8 TERMINAL TYPES 56 4 ELECTRICAL CHARACTERISTICS 60 4 1 ABOULUTE MAXIMUM RATINGS 60 4 2 RECOMMENDED OPERATING CONDITIONS 60...

Page 4: ...ry map in addition to simple instruction set 1 1 FEATURES GMS81508 GMS81516 ROM Bytes 8K 16K RAM Bytes 448 bytes includes stack area Execution Time 0 5us Xin 8MHz Basic Interval Timer 8bit 1ch Watch D...

Page 5: ...ROM 8 16K BYTE PRESCALER B I T R6 PORT R5 PORT R4 PORT R3 PORT R2 PORT R1 PORT R0 PORT AVref AVss R60 R67 AN0 AN7 R57 PWM1 R55 BUZ R56 PWM0 R54 WDTO R53 Srdy R52 Sclk R51 Sout R50 Sin R47 T3 O R46 T1...

Page 6: ...29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MP MODE 64 SDIP GMS81508 16 R65 AN5 R64 AN4 R63 AN3 R62 AN2 R61 AN1 R60 AN0 R57 PWM1 R56 PW...

Page 7: ...R60 AN0 R57 PWM1 R56 PWM0 R55 BUZ R54 WDTO R53 SRDY R52 SCLK R51 SOUT R50 SIN R47 T3O R46 T1O R45 EC2 R44 EC0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R37 R36 R35 R34 R33 R32 R31 R30 VDD MP AVSS AVREF...

Page 8: ...0 0 205 max 0 022 0 016 0 050 0 030 0 070 BSC 0 140 0 120 min 0 015 0 680 0 660 0 750 BSC 0 15 0 012 0 008 64SDIP 20 10 19 90 24 15 23 65 18 15 17 65 14 10 13 90 3 18 max 0 50 0 35 1 00 BSC SEE DETAIL...

Page 9: ...HYUNDAI MicroElectronics 1 60 max SEE DETAIL A 0 75 0 45 0 7 0 15 0 05 1 00 REF DETAIL A UNIT MM 10 00 BSC 12 00 BSC 12 00 BSC 10 00 BSC 0 38 0 22 0 50 BSC 1 45 1 35 64LQFP 4 1...

Page 10: ...o the Xin pin and the Xout pin should be left open 24 EC0 I Event Counter Source Clock Input Pin Timer 23 EC2 I 22 T1O O Timer Counter Overflow Output Pin 21 T3O O 28 INT0 I Ext Interrupt 27 INT1 I Ex...

Page 11: ...wer address output pins A0 A7 33 40 R20 R27 I O R2 Port Can be determined I O by R2DD In MP mode This functions as 8 bit higher address output pins A8 A15 I O Port 57 64 R30 R37 I O R3 Port Can be det...

Page 12: ...ounter PC consists of 16 bit registers The contents of these registers are undefined after RESET Program Counter 15 8 PCH 7 0 PCL A Register 7 0 A 15 8 Y YA 16bit Accumulator 7 0 A X Register 7 0 X Y...

Page 13: ...gister In case of 16 bit operation instruction this register has upper 8 bit of YA 16 bit accumulator In case of multiplication instruction MUL this register is executed as a multiplicand register Aft...

Page 14: ...outine CALL RET PUSH A X Y PSW POP A X Y PSW M sp PCH sp sp 1 M sp PCL sp sp 1 M sp A M sp PCH sp sp 1 M sp PCL sp sp 1 M sp PSW sp sp 1 sp sp 1 sp sp 1 PCL M sp sp sp 1 PCH M sp sp sp 1 A M sp PSW M...

Page 15: ...direct access for setting and resetting it can be used as a 1 bit accumulator It is a branch condition flag of BCS BCC instructions Zero Flag Z After an operation including 16 bit operation it is set...

Page 16: ...ctions when one word is added or subtracted in binary with the sign When results exceeds 127 or 128 this flag is set When BIT instruction is executed The bit6 of memory is input into V flag This flag...

Page 17: ...l RAM is used for data storage subroutine calling or stack area when interrupts occur When RAM is used as the stack area the depth of the subroutine nesting and the interrupt levels should be kept in...

Page 18: ...E3H not used FFC4H FFC5H TCALL 13 FFE4H FFE5H Serial I O FFC6H FFC7H TCALL 12 FFE6H FFE7H Basic Interval Timer FFC8H FFC9H TCALL 11 FFE8H FFE9H Watch Dog Timer FFCAH FFCBH TCALL 10 FFEAH FFEBH A D Con...

Page 19: ...W Undefined 00CBH R5 PORT I O DIRECTION REGISTER R5DD W 0 0 0 0 0 0 0 0 00CCH R6 PORT DATA REGISTER R6 R W Undefined 00CDH R6 PORT I O DIRECTION REGISTER R6DD W 0 0 0 0 00D0H PORT R4 MODE REGISTER PM...

Page 20: ...TROL REGISTER PWMCR W 00 00F3H INTERRUPT MODE REGISTER IMOD R W 0 0 0 0 0 0 00F4H INTERRUPT ENABLE REGISTER LOW IENL R W 0 0 0 0 00F5H INTERRUPT REQUEST FLAG REGISTER LOW IRQL R W 0 0 0 0 00F6H INTERR...

Page 21: ...R 6 2 3 1 Oscillation Circuit The clock signal incoming from crystal oscillator or ceramic resonator via Xin and Xout or from external clock via Xin is supplied to Clock Pulse Generator and Prescaler...

Page 22: ...S8 PS9 PS10 PS11 Interval 4 2 1 500 250 125 62 5 31 25 15 36 7 18 3 59 Period 250 500 1 2 4 8 16 32 64 128 256 The peripheral clock supplied from prescaler can be stopped by ENPCK However PS11 cannot...

Page 23: ...ate after Reset of BTCL is 0 The input clock of Basic Interval Timer is selected by BTS2 BTS0 Bit2 0 of CKCTLR among the prescaler outputs PS4 PS11 The Basic Interval Timer Register BITR can be read T...

Page 24: ...g Function 2 5 1 Control of Watch Dog Timer It can be used as 6 bit timer or WDT according to bit5 WDTON of Clock Control Register CKCTLR The counter can be cleared by setting WDTCL Bit 6 of WDTR and...

Page 25: ...2 BTS1 BTS0 B I T Input Clock The cycle of B I T The cycle of W D T max 0 0 0 PS4 2 512 32 256 0 0 1 PS5 4 1 024 64 512 0 1 0 PS6 8 2 048 129 024 0 1 1 PS7 16 4 096 258 048 1 0 0 PS8 32 8 192 516 096...

Page 26: ...Mode of Timer Timer0 Timer2 Timer1 Timer3 8 bit Interval Timer 8 bit Event Counter 8 bit input capture 8 bit Interval Timer 8 bit rectangular pulse output 16 bit Interval Timer 16 bit Event Counter 8...

Page 27: ...T0SL1 T2SL1 0 0 T0SL0 T2SL0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W T0 Start Stop control 0 Count Stop 1 Counting start after clearing T0 T2 Start Stop control 0 Count Stop 1...

Page 28: ...selected as input clock of T1 Timer0 1 operates as 16 bit timer In this case Timer0 1 only is controlled by T0ST T0CN and the interrupt vector is Timer0 vector The operation of T0 T1 is controlled by...

Page 29: ...er bit4 bit5 of PMR4 is set to 1 TDR value should be initialized to FFH because timer is cleared when it equals to TDR value but if you want to use interrupt TDR value should be written to 1H FFH 2 6...

Page 30: ...T R4 MODE REGISTER 00D0H PMR4 7 T3S 6 T1S 5 EC2S 4 EC0S 3 INT3S 2 INT2S 1 INT1S 0 INT0S W W W W W W W W R44 EC0 Selection 0 R44 Input Output 1 EC0 Input R45 EC2 Selection 0 R45 Input Output 1 EC2 Inpu...

Page 31: ...EGISTER 00D0H PMR4 7 T3S 6 T1S 5 EC2S 4 EC0S 3 INT3S 2 INT2S 1 INT1S 0 INT0S W W W W W W W W R40 INT0 Selection 0 R40 Input Output 1 INT0 Input R43 INT3 Selection 0 R43 Input Output 1 INT3 Input R41 I...

Page 32: ...analog input is selected by bit2 4 of A D Converter Mode Register ADCM This bits chooses among AN0 AN7 The other analog pins which are not used not A D conversion be used as normal port The A D Conve...

Page 33: ...erter 1 Enable A D Converter A D Conversion Start bit 0 invalid 1 Start A D Conversion after 1 cycle be cleared to 0 00E8H ADCM 7 6 5 4 ADS2 ADEN 3 ADS1 2 ADS0 1 ADST 0 ADSF R W R W R W R W R W R A D...

Page 34: ...register serial I O mode register clock selection circuit octal counter and control circuit SIOR 1 0 3 2 5 4 7 6 Sclk Octal Counter Control Circuit Internal Data BUS Internal Data BUS SM0 SM1 Srdy Srd...

Page 35: ...W R W R W At transmittion Sending Data at Sending Mode Receiving Data at Receiving Mode 00EAH SIOM 7 6 Srdy 5 SM1 4 SM0 3 SCK1 2 SCK0 1 SIOST 0 SIOSF R W R W R W R W R W R W R Serial Transmission Cloc...

Page 36: ...al I O 2 9 2 The Serial I O operation by Srdy pin transmission clock external clock The Srdy pin becomes L by SIOST 1 This signal tells to the external system that this device is ready for serial tran...

Page 37: ...ormed simultaneously it would be made error The SIO interrupt is generated at the completion of SIO and SIOSF is set to 1 In SIO interrupt service routine correct transmission should be tested In case...

Page 38: ...Control Register PWMCR and the width of pulse is determined by the PWM Register PWMR The pulse period according to input clock are as follows Input clock PWM Period PS8 32 8 192 PS9 64 16 384 PS10 12...

Page 39: ...K1 6 PICK0 5 P0CK 1 4 P0CK 0 3 EN1 2 EN0 1 POL1 0 POL0 W W W W W W W W PWM Enable Flag 00 Disable 01 PWM0 10 PWM1 11 PWM0 PWM1 PWM1 Clock Selection 00 PS8 01 PS9 10 PS10 11 PS11 PWM0 Clock Selection 0...

Page 40: ...river by setting bit5 of PMR5 00D1H to 1 BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0 MUX 0 1 2 3 4 5 T Q PS4 PS5 PS6 PS7 6 Buzzer Output 6bit Counter WtBUR Internal Data Bus PORT R5 MODE REGISTER BUZZER DATA...

Page 41: ...26 13 888 12 5 11 364 10 416 9 616 8 928 8 334 7 812 7 352 6 944 6 579 6 25 5 952 5 682 5 434 5 208 5 4 808 4 630 4 464 4 310 4 166 4 032 3 906 62 5 31 25 20 834 15 626 12 5 10 416 8 928 7 812 6 944 6...

Page 42: ...Interrupt Enable Register IENH IENL Interrupt Request Register IRQH IRQL priority circuit and selecting circuit The configuration of Interrupt circuit is shown in below 12 IRQL IRQH 4 7 7 0 RESET IFT...

Page 43: ...H Interrupt 6 T0R Timer 0 FFF3H FFF2H 7 T1R Timer 1 FFF1H FFF0H 8 T2R Timer 2 FFEFH FFEEH 9 T3R Timer 3 FFEDH FFFCH 10 AR A D Converter FFEBH FFEAH 11 WDTR Watch Dog Timer FFE9H FFE8H 12 BITR Basic In...

Page 44: ...e sampling point the interrupt having the higher priority is accepted The interrupt priority is determined by H W however multiple priority processing through software is possible by using interrupt c...

Page 45: ...rupt service routine is executed In the interrupt service routine the corresponding interrupt request flag is cleared and interrupt master enable flag I flag becomes 0 thereby another interrupts are n...

Page 46: ...rocessing step is determined by B Flag as a below Execution of BRK TCALL0 0 BRK or TCALL0 1 TCALL 0 Routine BRK Interrupt Routine RET B Flag RETI V L System Clock Instruction Fetch sp 2 new pc V H V L...

Page 47: ...flag must be cleared by EI instruction within the interrupt routine Then The higher priority interrupt is accepted among the interrupts that interrupt request flag is 1 Interrupt Mode Register IMOD i...

Page 48: ...multiple interrupts nest H W priority accept mode Mode0 and S W selection accept mode Mode1 EI EI EI Main Program Mode 0 1 st INT Routine Mode 0 2 nd INT Routine Mode 0 3 rd INT Routine Interrupt Inte...

Page 49: ...al Function STOP Mode Oscillator CPU Clock RAM Register Retain I O Port Retain Prescaler Basic Interval Timer Serial I O Operation External Clock Selection WDT Timer A DC PWM Buzzer Driver Address Bus...

Page 50: ...ted after stabilization oscillation time set by program After releasing STOP mode instruction execution is different by I Flag bit 2 of PSW If I Flag 1 entered Interrupt Service Routine If I Flag 0 ex...

Page 51: ...B I T clock for oscillation stabilization time Otherwise It is possible to release by only RESET input Because STOP mode is released by interrupt even if both of interrupt enable bit IE and interrupt...

Page 52: ...SET terminal is organized as schmitt input If initial value is undefined it is needed initialize by a S W RESET Operation Timing Opcode System Clock Instruction Fetch Start FFFF FFFE Address Bus FE AD...

Page 53: ...evel of the pin due to output loading Because the programmed input pin is floating the value of the pin can be read correctly When data is written to the programmed input pin it is written only to the...

Page 54: ...d of 8 bit programmable I O pin Register Name Symbol R W Address Initial Value R0 I O Direction Register R1DD W 00C3H 0000 0000 R0 PORT Data Register R1 R W 00C2H Not initialized R1 PORT I O DIRECTION...

Page 55: ...f 8 bit programmable I O pin Register Name Symbol R W Address Initial Value R2 I O Direction Register R2DD W 00C5H 0000 0000 R2 PORT Data Register R2 R W 00C4H Not initialized R2 PORT I O DIRECTION RE...

Page 56: ...Port is composed of 8 bit programmable I O pin Register Name Symbol R W Address Initial Value R3 I O Direction Register R3DD W 00C7H 0000 0000 R3 PORT Data Register R3 R W 00C6H Not initialized R3 PO...

Page 57: ...alt input pin 3 5 R4 PORT R4 Port is composed of 8bit programmable I O port and this port are double functional pin Register Name Symbol R W Address Initial Value R4 I O Direction Register R4DD W 00C9...

Page 58: ...R44 EC0 Selection 0 R44 Input Output 1 EC0 Input R47 T3 Selection 0 R47 Input Output 1 T3 Output R46 T1 Selection 0 R46 Input Output 1 T1 Output R40 INT0 Selection 0 R40 Input Output 1 INT0 Input R41...

Page 59: ...Direction Register R6DD W 00CDH 0000 R6 Port Data Register R6 R W 00CCH Not initialized A D Converter Mode Register ADCM W 00E8H 00 0001 Port R5 Output Data 00CAH R5 7 R57 6 R56 5 R55 4 R54 3 R53 2 R5...

Page 60: ...rcuit In input mode the pin impedance viewing from external MCU is very high that the current doesn t flow But input voltage level should be VSS or VDD Be careful that if unspecified voltage i e if un...

Page 61: ...MicroElectronics 56 3 8 TERMINAL TYPES PIN TERMINAL TYPE Xin Xout RESET MP R00 R07 Rd Data Bus Vss Data Bus 1 MUX 0 MUX Direction REG Vdd Data Bus Data Bus Data REG MP Rd Data Bus Xin Xout Vdd Vss ST...

Page 62: ...s Vss MUX MUX Vdd MP From R30 Rd From R31 Wt From R32 R W From R33 C From R34 SYNC From R35 BAK Data REG Direction REG Rd Data Bus Data Bus Data Bus Vss MUX Vdd MP Data REG Direction REG Rd to BRQ to...

Page 63: ...lection Data Bus Data REG Direction REG Rd To R40 INT0 To R41 INT1 To R42 INT2 To R43 INT3 To R44 EC0 To R45 EC2 To R50 Sin Data Bus Vss Data Bus MUX Vdd Selection Data Bus Data REG Direction REG Rd D...

Page 64: ...63 AN3 R64 AN4 R65 AN5 R66 AN6 R67 AN7 Rd Srdy o Srdy in Data Bus Data Bus Data Bus Vss MUX MUX Vdd Selection Srdy Data REG Direction REG To A D Converter Data Bus Vss Data Bus MUX Direction REG Vdd D...

Page 65: ...MENDED OPERATING CONDITIONS Parameter Symbol Unit Specifications Min Typ Max Supply Voltage Vdd V 4 5 5 5 Operating Frequency fXin MHz 1 8 Operating Temperature Topr C 20 85 4 3 A D CONVERTER CHARACTE...

Page 66: ...dd L Input voltage Vil R0 R1 R2 R3 V 0 0 3Vdd Xin 0 0 1Vdd H Input Leakage Current Iih all input pins Vi Vdd 5 5 L Input Leakage Current Iil all input pins Vi Vss 5 5 H output Voltage Voh R0 R1 R2 R3...

Page 67: ...ut tST ms 20 External Clock Pulse Width Xin tcpw ns 100 External Clock Transition Time Xin trcp tfcp ns 20 Interrupt Pulse Width INT0 INT3 tIW tsys 2 RESET Input L Width RESET tRST tsys 8 Event Counte...

Page 68: ...Sin tfsin trsin ns 30 Sin Input Setup time Exnternal Sclk Sin tsus ns 100 Sin Input Setup time Internal Sclk Sin tsus ns 200 Sin Input Hold Time Sin ths ns tsys 70 Serial Output Clock Cycle Time Sclk...

Page 69: ...ata Output Hold Time D0 D7 thw ns 20 Data Input Setup Time D0 D7 tsuR ns 80 Data Input Hold Time D0 D7 thR ns 15 Rd Output Delay Time Rd tdRd tsys 90 Wt Output Delay Time Wt tdWt tsys 130 R W Output D...

Page 70: ...tsys 100 BAK Delay Time BAK tdBA tsys 50 BAK Release Delay Time BAK tdRBA tsys 220 Bus Address Data Control Release Delay Time D0 D7 A0 A15 Rd Wt R W tdRA tsys 210 Timing Chart Instruction Ececution...

Page 71: ...17 ASL A 08 1 2 Arithmetic shift left 18 ASL dp 09 2 4 C 7 6 5 4 3 2 1 0 N ZC 19 ASL dp X 19 2 5 20 ASL abs 18 3 5 21 CMP imm 44 2 2 Compare accumulator contents with memory contents 22 CMP dp 45 2 3...

Page 72: ...54 INC dp 89 2 4 M M 1 N Z 55 INC dp X 99 2 5 N Z 56 INC abs 98 3 5 N Z 57 INC X 8F 1 2 N Z 58 INC Y 9E 1 2 N Z 59 LSR A 48 1 2 Logical shift right 60 LSR dp 49 2 4 7 6 5 4 3 2 1 0 C N ZC 61 LSR dp X...

Page 73: ...2 Load accumulator 2 LDA dp C5 2 3 A M 3 LDA dp X C6 2 4 4 LDA abs C7 3 4 5 LDA abs Y D5 3 5 N Z 6 LDA dp X D6 2 6 7 LDA dp Y D7 2 6 8 LDA X D4 1 3 9 LDA X DB 1 4 X register auto increment A M X X 1...

Page 74: ...ontents to accumulator A Y N Z 39 XAX EE 1 4 Exchange X register contents with accumulator X A 40 XAY DE 1 4 Exchange Y register contents with accumulator Y A 41 XMA dp BC 2 5 Exchange memory contents...

Page 75: ...4B 3 5 Bit complement M bit M bit 15 OR1 M bit 6B 3 5 Bit OR C flag C C M bit C 16 OR1B M bit 6B 3 5 Bit OR C flag and NOT C C M bit C 17 SET1 dp bit x1 2 4 Set bit M bit 1 18 SETA1 A bit 0B 2 2 Set A...

Page 76: ...pc pc rel 14 CALL abs 3B 3 8 Subroutine call 15 CALL dp 5F 2 8 M sp pcH sp sp 1 M sp pcL sp sp 1 if abs pc abs if dp pcL dp pcH dp 1 16 CBNE dp rel FD 3 5 7 Compare and branch if not equal 17 CBNE dp...

Page 77: ...FF 1 2 No operation 5 POP A 0D 1 4 sp sp 1 A M sp 6 POP X 2D 1 4 sp sp 1 X M sp 7 POP Y 4D 1 4 sp sp 1 Y M sp 8 POP PSW 6D 1 4 sp sp 1 PSW M sp restored 9 PUSH A 0E 1 4 M sp A sp sp 1 10 PUSH X 2E 1 4...

Page 78: ...ode Quick Pulse Mode When user use general EPROM programmer socket adaper is essencially required It convert pin to fit the pin of general 27C256 EPROM Three type socket adapters are provided accordin...

Page 79: ...GMS81516AT PROGRAMMING MANUAL...

Page 80: ...ides a highly flexible and cost effective solution to many embedded control applications The GMS81516AT provides the following standard features 16K bytes of EPROM 448 bytes of RAM 56 I O lines 16 bit...

Page 81: ...64LQFP 64QFP GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics 3...

Page 82: ...24 R44 EC0 I O OE I 25 R43 INT3 I O 1 I 26 R42 INT2 I O 1 I 27 R41 INT1 I O 1 I 28 R40 INT0 I O 1 I 29 RESET I 1 I 30 XIN I 1 I 31 XOUT O 3 O 32 VSS VSS Pin No MCU Mode OTP Mode 33 R27 I O A15 I 34 R2...

Page 83: ...T0 I O 1 I 23 RESET I 1 I 24 XIN I 1 I 25 XOUT O 3 O 26 VSS VSS 27 R27 I O A15 I 28 R26 I O A14 I 29 R25 I O A13 I 30 R24 I O A12 I 31 R23 I O A11 I 32 R22 I O A10 I Pin No MCU Mode OTP Mode 33 R21 I...

Page 84: ...23 XOUT O 3 O 24 VSS VSS 25 R27 I O A15 I 26 R26 I O A14 I 27 R25 I O A13 I 29 R24 I O A12 I 29 R23 I O A11 I 30 R22 I O A10 I 31 R21 I O A9 I 32 R20 I O A8 I Pin No MCU Mode OTP Mode 33 R17 I O A7 I...

Page 85: ...C000H to FFFFHof the OTP device 1 The data format to be programmed is made up of Motorola S1 format Ex Motorola S1 format S0080000574154434880 S1244000E1FF3BFF04A13F8F06E101711B821B1BE01D1B3B191BF6181...

Page 86: ...C4 00 FC 5E C0 70 67 C0 00 C0 C000H C001H C002H C003H C004H C005H C006H C007H FFF2H FFF3H FFFEH FFFFH Reading Verify Up Loading Data Address Data Address Data Programmer Buffer Checksum E1 FF 3B FF 04...

Page 87: ...it Test condition VPP Intelligent Programming 12 0 13 0 V VDD 1 Intelligent Programming 5 75 6 25 V IPP 2 VPP supply current 50 mA CE VIL IDD 2 VDD supply current 30 mA VIH Input high voltage 0 8 VDD...

Page 88: ...t tDH Addresses OE Output High Z VIH VIL VIH VIL VIH VIL tAS 2 READING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be steady May change from H to L May change from L to H Do not care any change permitted D...

Page 89: ...DFP Addresses Data High Z VIH VIL 12 5V VDD VPP VDD CE OE 6 0V 5 0V tAS tDS tVPS tVDS tOPW tPW tOES Program Program Verify tDH VIH VIL VIH VIL VIH VIL tAH Address Stable Data In Stable Data out Valid...

Page 90: ...H Data hold time 1 us tDFP Output disable delay time 0 us tVPS VPP setup time 2 us tVDS VDD setup time 2 us tPW Program pulse width 0 95 1 0 1 05 ms Intelligent tOPW CE pulse width when over programmi...

Page 91: ...RESS VDD VPP 5 0V COMPARE ALL BYTES TO ORIGINAL DATA DEVICE PASSED INCREMENT ADDRESS YES NO FAIL PASS FAIL PASS NO YES FAIL PASS DEVICE FAILED PROGRAM ONE PULSE OF 3X msec DURATION X 25 ADDRESS FIRST...

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