No.
Name
Description
5
Air deflector
Directs air flows to reduce the CX116 temperature and
achieve optimal heat dissipation of the PHY module.
6
Captive screw
Secures the CX116.
7
Ejector lever
-
8
GE electrical port
module
Provides 32 x 1000 Base-T Ethernet electric ports (RJ45)
on the CX116. Each port provides a green indicator.
1.6 Architecture
This topic describes the CX116 logical architecture.
The CX116 logical architecture includes the processor module, CPLD module, PHY module,
and GE pass through module.
l
Processor module: The processor module, in a dominant frequency of 333 MHz, is the
controlling core for the CX116 and supports master/slave and multi-master modes.
l
CPLD module: The CPLD module is a key module to help the processors to collect the
CX116 information, and power on, power off, and reset the CX116.
l
PHY module: The PHY module converts the 32 Serdes signals to 32 x 1000 BASE-T
signals.
Figure 1-9
Logical architecture
Main Board
CPLD
Front Panel
Backplane
Four PHY modules
CPU
EEPROM
DDR2
PWR
HLY
Flash
32 x RJ45
16*(2*GE)
16*(2*GE)
Huawei CX116 Pass Through Module
White Paper
1 Overview
Issue 05 (2017-03-27)
Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
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