FRAM71B
User’s Manual
FRAM71B 1.00
- 15 -
©Hans Brueggemann, 2016
9.1 Configuration Strings
There are two options of using Chips as Memory Modules (MM):
1. Use a single Chip per MM by putting either
•
"A" for 16 K, or
•
"9" for 32 KByte in BOT FRAM, or
•
"B" for 32 KByte in TOP FRAM
1)
at the respective configuration address.
2. Use multiple Chips in a daisy-chain configuration and manage them as one MM. In
this case, the MM consists of multiple Chips that are not "Last Chip in Module”, fol-
lowed by one Chip that is "LCIM”.
To inspect the current configuration of your FRAM71B, key in [PEEK$] ("2C000",32)
[ENDLINE] to get "c
0
f
0
c
1
f
1
… c
15
f
15
", where c
x
is the configuration nibble and f
y
is the base
address of Chip_x as described in table 2 and 3.
To alter the configuration, key in [POKE] "2C000”, "c
0
f
0
c
1
f
1
… c
15
f
15
" [ENDLINE].
Then key in [f] [OFF] [ON] to announce the altered configuration to the OS. The power cy-
cling is required because FRAM71B has no way to access the "MODULE PULL” mechanism.
v
The configuration area C_0x2C010 - C_0x2C01F is shared with internal experimental
registers. If the actual memory configuration is less than eight chips,
PEEK$("2C000”,32) will return status information of those registers in the last eight
nibbles, for example "93 94 95 96 00 00 00 00 10 00 10 10 10 10 10 10". These can be
safely ignored.
9.2 Examples
"00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00": (32 zeroes)
0 K + 16 K = 16 KByte. This is the standard HP-71B RAM configuration when there is no other
MM and FRAM71B is not configured.
"93 94 A5 00 …":
2 x 32 K + 1 x 16 K + 16 K = 96 KByte.
PORT(5.00): 32k RAM
MM_0, Chip_0, 32 K, LCIM, RAM
PORT(5.01): 32 k RAM
MM_1, Chip_1, 32 K, LCIM, RAM
PORT(5.02): 16 k RAM
MM_2, Chip_2, 16 K, LCIM, RAM
9.3 Maximum Memory
The maximum achievable memory configuration is shown in the following example:
"13 14 15 16 17 18 19 1A 1B 9C 9D AE 00 …":
10 x 32 K + 1 x 32 K + 1 x 16 K + 16 K = 384 KByte.
PORT(5.00): 320 K RAM
MM_0, Chip_0 .. 8, 9 x 32 K, RAM, Chip_9, 1 x 32 K, LCIM, RAM
PORT(5.01): 32 K RAM
MM_1, Chip_10, 32 K, LCIM, RAM
