HP E2466C, User Manual

Page: 59 / 93

Modes of operation
The preprocessor interface can operate in State mode or Timing mode. In
State mode, the logic analyzer master clock is always qualified with the
"cqual#" signal from the preprocessor. This clock qualifier is set to either
Compacted or Expanded. By eliminating idle clocks, the Compacted qualifier
can potentially capture many more transactions than the Expanded qualifier.
Refer to chapter 1 for information on configuring the preprocessor interface
and logic analyzer for the desired mode of operation.
State Mode Operation
State mode uses the BCLK rising edge to capture the signals from the
Pentium II processor bus and to clock the logic analyzer. A PLD in the
preprocessor generates additional information about each clock. The PLD
information along with the bus signals are sent to the logic analyzer and used
by the transaction tracker and inverse assembler to produce the transaction
display (see Figure 21, Block Diagram).
Pentium II processor signals require a three-clock latency to move the
information from the processor pins to the logic analyzer memory (except for
the three bus signals on connector P1, which only require two clocks). The
first clock is used to capture all of the bus signals in latches on the
preprocessor. The second clock is used to move the bus signals from the
preprocessor latches into the logic analyzer slave register. The slave latches
exists within the logic analyzer, not in the preprocessor. Also, on the second
clock, the PLD uses the signals that were captured on the first clock to
generate additional information. The third clock is used by the logic analyzer
to trigger on and/or store the data and the PLD information.
The preprocessor interface captures but does not display the REQ[4:0]# bus
signal group.
State Mode Clocking
To utilize the logic analyzer slave latches, the logic analyzer is configured to
operate in "master/slave" mode. The logic analyzer uses the BCLK [L
↑
] to
capture all pod data, except the pod connected to preprocessor connector
P1, in the slave register. Connector P1 carries the PLD signals and is
Preprocessor Interface Hardware Reference
Modes of operation
3-6 Preprocessor Interface for the Pentium II Processor