HP 600 Series, Services And Applications

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Multiprocessor and Memory Architecture
The key feature of the HP Router 650 is its pipelined multiprocessor
architecture. The routing engine uses the 33-megahertz Intel i960 CF RISC
processor to handle network-layer protocol routing. Each interface card,
here called a Data Link Accelerator (DLA) module, also uses a 33-megahertz
Intel i960 CF RISC processor to offload the routing engine from the data-link-
layer-specific tasks, such as header preprocessing, tabulating data-link-layer
counters, token-ring source routing, filtering, and EASE sampling. WAN DLA
modules handle PPP, frame relay, X.25, ISDN, SMDS, and compression as
well.
Figure 3. Logical View of Router Series 600 Architecture
The high-speed multiported memory architecture allows the DLA modules to
access packets at the same time as the routing engine does, with no
degradation in performance. The backplane allows each DLA module to
access the multiported packet memory. The memory bus is dedicated solely
to switching packets in a cell-interleaved manner, to ensure equitable bus
utilitization and to minimize buffering latency.
In addition to the memory bus, the DLA modules also attach to a
management bus, used for interprocessor communication and for tasks such
as link status notification, “hot swapping” (online replacement of modules),
configuration, and all nonswitching tasks.
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Architecture and Technology
Router 650 Hardware
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