Rev. 1.20
38
November 20, 2019
Rev. 1.20
39
November 20, 2019
HT66F2740
12V High Current Flash MCU
HT66F2740
12V High Current Flash MCU
Writing Data to the EEPROM
To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in
the EEA register and the data placed in the EED register. To initiate a write cycle, the write enable
bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR
bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions
must be executed in two consecutive instruction cycles. The global interrupt bit EMI should also
first be cleared before implementing any write operations, and then set again after the write cycle
has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has
not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is
asynchronous to microcontroller system clock, a certain time will elapse before the data will have
been written into the EEPROM. Detecting when the write cycle has finished can be implemented
either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write
cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing
the user that the data has been written to the EEPROM. The application program can therefore poll
the WR bit to determine when the write cycle has ended.
Write Protection
Protection against inadvertent write operation is provided in several ways. After the device is
powered-on the Write Enable bit in the control register will be cleared preventing any write
operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset
to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control register
is located in Sector 1, this adds a further measure of protection against spurious write operations.
During normal program operation, ensuring that the Write Enable bit in the control register is
cleared will safeguard against incorrect write operations.
EEPROM Interrupt
The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM
interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an
EEPROM write cycle ends, the DEF request flag will be set. If the
global and EEPROM interrupt is
enabled and the stack is not full, a jump to the associated EEPROM Interrupt vector will take place.
When the interrupt is serviced, the EEPROM interrupt request flag, DEF, will be automatically
reset and the EMI bit will be automatically cleared to disable other interrupts. More details can be
obtained in the Interrupt section.
Programming Considerations
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be
enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also
the Memory Pointer high byte register, MP1H or MP2H, could be normally cleared to zero as this
would inhibit access to Sector 1 where the EEPROM control register exist. Although certainly not
necessary, consideration might be given in the application program to the checking of the validity of
new write data by a simple read back process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high,
to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared
before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device
should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally
complete. Otherwise, the EEPROM read or write operation will fail.