Rev. 1.20
138
November 20, 2019
Rev. 1.20
139
November 20, 2019
HT66F2740
12V High Current Flash MCU
HT66F2740
12V High Current Flash MCU
pin function is disabled by clearing the UMD, UREN, UTXEN or URXEN bit, the TX or RX pin
will be set to a floating state. At this time whether the internal pull-high resistor is connected to the
TX or RX pin or not is determined by the corresponding I/O pull-high function control bit.
UART Data Transfer Scheme
The above block diagram shows the overall data transfer structure arrangement for the UART. The
actual data to be transmitted from the MCU is first transferred to the UTXR_RXR register by the
application program. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only
the UTXR_RXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not
mapped and is therefore inaccessible to the application program.
Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB
first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift
register is full, the data will then be transferred from the shift register to the internal UTXR_RXR
register, where it is buffered and can be manipulated by the application program. Only the UTXR_RXR
register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is
therefore inaccessible to the application program.
It should be noted that the actual register for data transmission and reception only exists as a single
shared register in the Data Memory. This shared register known as the UTXR_RXR register is used
for both data transmission and data reception.
UART Status and Control Registers
There are six control registers associated with the UART function. The UMD bit in the SIMC0
register can be used to select the UART mode. The UUSR, UUCR1 and UUCR2 registers control
the overall function of the UART, while the UBRG register controls the Baud rate. The actual data
to be transmitted and received on the serial interface is managed through the UTXR_RXR data
register. Note that UART related registers and their POR values are only available when the UART
mode is selected by setting the UMD bit in the SIMC0 register to “1”.
Register
Name
Bit
7
6
5
4
3
2
1
0
SIMC0
SIM2
SIM1
SIM0
UMD
SIMDEB1 SIMDEB0 SIMEN
SIMICF
UUSR
UPERR
UNF
UFERR UOERR URIDLE
URXIF
UTIDLE
UTXIF
UUCR1
UREN
UBNO
UPREN
UPRT
USTOPS UTXBRK
URX8
UTX8
UUCR2
UTXEN
URXEN UBRGH UADDEN UWAKE
URIE
UTIIE
UTEIE
UTXR_RXR UTXRX7 UTXRX6 UTXRX5 UTXRX4 UTXRX3 UTXRX2 UTXRX1 UTXRX0
UBRG
UBRG7
UBRG6
UBRG5
UBRG4
UBRG3
UBRG2
UBRG1
UBRG0
UART Register List
• SIMC0 Register
Bit
7
6
5
4
3
2
1
0
Name
SIM2
SIM1
SIM0
UMD
SIMDEB1 SIMDEB0 SIMEN
SIMICF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
0
0
0
0
0
Bit 7~5
SIM2~SIM0
: USIM SPI/I
2
C Operating Mode Control
When the UMD bit is cleared to zero, these bits setup the SPI or I
2
C operating mode of
the USIM function. Refer to the SPI or I
2
C register section for more details.