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Holtek HT66F2740 Manual Download Page 133

Rev. 1.20

132

November 20, 2019

Rev. 1.20

133

November 20, 2019

HT66F2740

12V High Current Flash MCU

HT66F2740

12V High Current Flash MCU

I

2

C Bus Start Signal

The START signal can only be generated by the master device connected to the I

2

C bus and not by 

the slave device. This START signal will be detected by all devices connected to the I

2

C bus. When 

detected, this indicates that the I

2

C bus is busy and therefore the HBB bit will be set. A START 

condition occurs when a high to low transition on the SDA line takes place when the SCL line 
remains high.

I

2

C Slave Address

The transmission of a START signal by the master will be detected by all devices on the I

2

C bus. 

To determine which slave device the master wishes to communicate with, the address of the slave 
device will be sent out immediately following the START signal. All slave devices, after receiving 
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by 
the master matches the internal address of the microcontroller slave device, then an internal USIM 
I

2

C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, 

defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave 
device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device 

will also set the status flag HAAS when the addresses match.

As an USIM I

2

C bus interrupt can come from three sources, when the program enters the interrupt 

subroutine, the HAAS and SIMTOF bits should be examined to see whether the interrupt source 
has come from a matching slave address or from the completion of a data byte transfer or from the 
I

2

C bus time-out occurrence. When a slave address is matched, the device must be placed in either 

the transmit mode and then write data to the SIMD register, or in the receive mode where it must 
implement a dummy read from the SIMD register to release the SCL line.

I

2

C Bus Read/Write Signal

The SRW bit in the SIMC1 register defines whether the master device wishes to read data from the 

I

2

C bus or write data to the I

2

C bus. The slave device should examine this bit to determine if it is to 

be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes 

to read data from the I

2

C bus, therefore the slave device must be setup to send data to the I

2

C bus as 

a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I

2

C 

bus, therefore the slave device must be setup to read data from the I

2

C bus as a receiver.

I

2

C Bus Slave Address Acknowledge Signal

After the master has transmitted a calling address, any slave device on the I

2

C bus, whose 

own internal address matches the calling address, must generate an acknowledge signal. The 
acknowledge signal will inform the master that a slave device has accepted its calling address. If no 
acknowledge signal is received by the master then a STOP signal must be transmitted by the master 

to end the communication. When the HAAS flag is high, the addresses have matched and the slave 
device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag 

is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register 

should be set to “1”. If the SRW flag is low, then the microcontroller slave device should be setup as 

a receiver and the HTX bit in the SIMC1 register should be cleared to “0”.

I

2

C Bus Data and Acknowledge Signal

The transmitted data is 8-bit wide and is transmitted after the slave device has acknowledged receipt 

of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After 

receipt of 8 bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can 
receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from 
the master receiver, then the slave transmitter will release the SDA line to allow the master to send 

Summary of Contents for HT66F2740

Page 1: ...12V High Current Flash MCU HT66F2740 Revision V1 20 Date November 20 2019 ...

Page 2: ...s 16 System Start Up Time Characteristics 16 Input Output Characteristics 17 Memory Characteristics 17 LVR LVD Electrical Characteristics 18 Internal Reference Voltage Characteristics 18 Over Voltage Protection Electrical Characteristics 19 High Voltage I O Electrical Characteristics 19 Voltage Detector Electrical Characteristics 19 High Voltage I O Other Electrical Characteristics 20 Low Dropout ...

Page 3: ...US 34 EEPROM Data Memory 36 EEPROM Data Memory Structure 36 EEPROM Registers 36 Reading Data from the EEPROM 37 Writing Data to the EEPROM 38 Write Protection 38 EEPROM Interrupt 38 Programming Considerations 38 Oscillators 40 Oscillator Overview 40 System Clock Configurations 40 Internal High Speed RC Oscillator HIRC 41 Internal 32kHz Oscillator LIRC 41 Operating Modes and System Clocks 41 System...

Page 4: ...ating Modes 74 Standard Type TM STM 80 Standard Type TM Operation 80 Standard Type TM Register Description 80 Standard Type TM Operation Modes 85 Periodic Type TM PTM 95 Periodic Type TM Operation 95 Periodic Type TM Register Description 95 Periodic Type TM Operation Modes 100 Over Voltage Protection OVP 109 Over Voltage Protection Registers 109 Input Offset Calibration 111 Low Dropout Regulator L...

Page 5: ...nterrupt 169 USIM Interrupt 169 Standard and Periodic Type TM Interrupts 169 LVD Interrupt 170 A D Converter Interrupt 170 EEPROM Interrupt 170 Time Base Interrupts 170 High Voltage Short Circuit Interrupt 172 Multi function Interrupt 172 Compact Type TM Interrupts 172 Interrupt Wake up Function 173 Programming Considerations 173 Configuration Options 174 Application Circuits 174 Instruction Set 1...

Page 6: ...MCU Instruction Definition 181 Extended Instruction Definition 190 Package Information 197 16 pin NSOP EP 150mil Outline Dimensions 198 24 pin SSOP EP 150mil Outline Dimensions 199 24 pin SOP 300mil Outline Dimensions 200 28 pin SOP 300mil Outline Dimensions 201 ...

Page 7: ...ipheral Features Flash Program Memory 4K 16 RAM Data Memory 256 8 True EEPROM Memory 128 8 Watchdog Timer function Up to 14 bidirectional I O lines 10 bidirectional High Voltage I O lines with short circuit protection function 2 pin shared external interrupts Multiple Timer Modules for time measurement capture input compare match output or PWM output or single pulse output function Over Voltage Pr...

Page 8: ...ich require no external components for their implementation The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption This device contains a programmable I O port source current function which is used to implement LED driving function The High Voltage I ...

Page 9: ...13 14 VCC2 PB3 PB4 PB0 PB2 PB1 PA3 INT1 PTPI SCS OVPI1 AN1 PD0 STPI SCS AN2 PA6 INT1 SDI SDA RX STP AN6 PA7 PTPI SDO TX PTP AN7 PA1 INT0 STPI SCK SCL OVPI0 AN0 PD1 STCK PTCK SDO TX AN3 PB7 PB6 PB5 CTP PA4 CTCK STCK PTCK SDI SDA RX VREF AN4 PA2 SDI SDA RX ICPCK OCDSCK PA0 SDO TX SCK SCL ICPDA OCDSDA PC1 PTP PC0 STP VCC1 PA5 INT0 SCK SCL STPB AN5 AVDD VDD VLDO AVSS VSS HVSS PD4 CTPB PTPB PD5 OVPCOUT...

Page 10: ...SDA PA0 PAPU PAWU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up SDO PAS0 CMOS SPI serial data output TX PAS0 CMOS UART data transmitter pin SCK PAS0 IFS0 ST CMOS SPI serial clock SCL PAS0 IFS0 ST NMOS I2 C clock line ICPDA ST CMOS ICP address data OCDSDA ST CMOS OCDS address data for EV chip only PA1 INT0 STPI SCK SCL OVPI0 AN0 PA1 PAPU PAWU PAS0 ST CMOS General purpose I O...

Page 11: ...PI serial data input SDA PAS1 IFS0 ST NMOS I2 C data line RX PAS1 IFS0 ST UART data receiver pin VREF PAS1 AN A D Converter external reference input AN4 PAS1 AN A D Converter external input channel 4 PA5 INT0 SCK SCL STPB AN5 PA5 PAPU PAWU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up INT0 PAS1 IFS1 ST External Interrupt 0 input SCK PAS1 IFS0 ST CMOS SPI serial clock SCL PA...

Page 12: ...ll up STPI PDS0 IFS1 ST STM capture input SCS PDS0 IFS0 ST CMOS SPI slave select AN2 PDS0 AN A D Converter external input channel 2 PD1 STCK PTCK SDO TX AN3 PD1 PDPU PDS0 ST CMOS General purpose I O Register enabled pull up STCK PDS0 IFS1 ST STM clock input PTCK PDS0 IFS0 ST PTM clock input SDO PDS0 CMOS SPI serial data output TX PDS0 CMOS UART data transmitter pin AN3 PDS0 AN A D Converter extern...

Page 13: ...age VSS AVSS HVSS VSS PWR Digital negative power supply AVSS PWR A D Converter negative power supply HVSS PWR High Voltage Power negative power supply VCC1 VCC1 PWR High Voltage Power for LDO input voltage VCC2 VCC2 PWR High Voltage Power for HVIO Level Shifter input voltage Legend I T Input type O T Output type OPT Optional by register option PWR Power ST Schmitt Trigger input CMOS CMOS output NM...

Page 14: ...bles note that factors such as oscillator type operating voltage operating frequency pin load conditions temperature and program instruction type etc can all exert an influence on the measured values Operating Voltage Characteristics Ta 40 C 85 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Operating Voltage HIRC fHIRC 8MHz 4 5 5 5 V fHIRC 12MHz 4 5 5 5 fHIRC 16MHz 4 5 5 5 Operating Volta...

Page 15: ...so the current consumption in the high voltage circuit should be added when the device is operating A C Characteristics For data in the following tables note that factors such as oscillator type operating voltage operating frequency and temperature etc can all exert an influence on the measured values High Speed Internal Oscillator HIRC Frequency Accuracy During the program writing operation the w...

Page 16: ... Unit VDD Conditions tSST System Start up Time Wake up from Condition where fSYS is Off fSYS fH fH 64 fH fHIRC 16 tSYS fSYS fSUB fLIRC 2 tSYS System Start up Time Wake up from Condition where fSYS is On fSYS fH fH 64 fH fHIRC 2 tSYS fSYS fSUB fLIRC 2 tSYS System Speed Switch Time FAST to SLOW Mode or SLOW to FAST Mode fHIRC switches from off on 16 tHIRC tRSTD System Reset Delay Time Reset Source f...

Page 17: ...VDD SLEDC m 1 m 10B m 0 2 4 6 3 6 7 3 VOH 0 9VDD SLEDC m 1 m 11B m 0 2 4 6 8 16 RPH Pull high Resistance for I O Ports Note 5V 10 30 50 kΩ ILEAK Input Leakage Current 5V VIN VDD or VIN VSS 1 μA tTCK TM TCK Input Pin Minimum Pulse Width 0 3 μs tTPI TM TPI Input Pin Minimum Pulse Width 0 3 μs tINT External Interrupt Minimum Pulse Width 10 μs Note The RPH internal pull high resistance value is calcul...

Page 18: ...ble voltage select 3 3V Ta 40 C 85 C 3 3 LVD enable voltage select 3 6V Ta 40 C 85 C 3 6 LVD enable voltage select 4 0V Ta 40 C 85 C 4 0 ILVRLVDBG Operating Current 5V LVD enable LVR enable VBGEN 0 20 25 μA LVD enable LVR enable VBGEN 1 180 200 μA tLVDS LVDO Stable Time For LVR enable VBGEN 0 LVD off on Ta 40 C 85 C 18 μs tLVR Minimum Low Voltage Width to Reset 120 240 480 μs tLVD Minimum Low Volt...

Page 19: ...ge for High Voltage I O Ports 0 7VIN VIN V VIL Input Low Voltage for High Voltage I O Ports 0 0 3VIN V IOH Source Current for High Voltage I O Ports VOH 0 9 VIN VIN 12V 60 120 mA IOL Sink Current for High Voltage I O Ports VOL 0 1 VIN VIN 12V 60 120 mA tSF Short Flag Response Time VIN 7 5V SFRTC 0 0 9 1 7 ms VIN 7 5V SFRTC 0 Ta 40 C 85 C 0 6 3 0 ms VIN 7 5V SFRTC 1 0 45 1 10 ms VIN 7 5V SFRTC 1 Ta...

Page 20: ...0mA 1 5 2 mV C ΔVOUT_RIPPLE Output Voltage Ripple 6V ILOAD 10mA 50 mV RR Ripple Rejection 4 VIN 10VDC 2VP P AC ILOAD 50mA f 120Hz 35 dB ILIMIT Current Limit 6V ΔVOUT 10 700 mA Note 1 Load regulation is measured at a constant junction temperature using pulse testing with a low ON time and is guaranteed up to the maximum power dissipation Power dissipation is determined by the input output different...

Page 21: ... less than 10Ω Aluminum electrolytic capacitor is suitable provided they meet the requirements described above For better load transient response purposes use a combination of a CLOAD 10μF and extra 0 1μF capacitor on VOUT Note that the 0 1μF capacitor is always required on VOUT and strong recommended be a multi layer ceramic capacitor The internal regulator is designed to be stable with an output...

Page 22: ...of microcontrollers is attributed to their internal system architecture The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped hence instructions are effectively executed in one or two cycl...

Page 23: ...xecute the branch The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications Fetch Inst PC System Clock fSYS Phase Clock T1 Phase Clock T2 Phase Clock T3 Phase Clock T4 Program Counter PC PC 1 PC 2 Pipelining Execute Inst PC 1 Fetch Inst PC 1 Execute Inst PC Fetch Inst PC 2 Execute Inst PC 1 System Clocking and Pipelining Fetch Inst 1 1 MOV A ...

Page 24: ...naled by a return instruction RET or RETI the Program Counter is restored to its previous value from the stack After a device reset the Stack Pointer will point to the top of the stack If the stack is full and an enabled interrupt takes place the interrupt request flag will be recorded but the acknowledge signal will be inhibited When the Stack Pointer is decremented by RET or RETI the interrupt w...

Page 25: ... convenience of code modification on the same device By using the appropriate programming tools the Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating Structure The Program Memory has a capacity of 4K 16 bits The Program Memory is addressed by the Program Counter and also contains data table i...

Page 26: ...hows how the table pointer and table data is defined and retrieved from the microcontroller This example uses raw table data located in the Program Memory which is stored there using the ORG statement The value at this ORG statement is 0F00H which refers to the start address of the last page within the 4K words Program Memory of the device The table pointer low byte register is setup here to have ...

Page 27: ... easy upgrades and modifications to their programs on the same device As an additional convenience Holtek has provided a means of programming the microcontroller in circuit using a 4 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming or upgrading the program at a later...

Page 28: ...evice to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT IDE development tools The OCDSDA pin is the OCDS Data Address input output pin while the OCDSCK pin is the OCDS clock input pin When users use the EV chip device for debugging the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in th...

Page 29: ...ogram control Switching between the different Data Memory sectors is achieved by properly setting the Memory Pointers to correct value if using the indirect addressing method Structure The Data Memory is subdivided into two sectors all of which are implemented in 8 bit wide RAM Each of the Data Memory Sector is categorized into two types the special Purpose Data Memory and the General Purpose Data...

Page 30: ...has 9 valid bits for this device the high byte indicates a sector and the low byte indicates a specific address General Purpose Data Memory All microcontroller programs require an area of read write memory where temporary data can be stored and retrieved for use later It is this area of RAM memory that is known as General Purpose Data Memory This area of Data Memory is fully accessible by the user...

Page 31: ...IMTOC UBRG SIMA SIMC2 UUCR2 SIMD UTXR_RXR SIMC1 UUCR1 SIMC0 PDC PD EEC 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 59H 58H 5BH 5AH 5DH 5CH 5FH 53H 54H 55H 56H 57H 5EH 60H 61H 62H 69H 68H 6BH 6AH 6DH 6CH 6FH 6EH 63H 64H 65H 66H 67H 70H 71H 72H 78H 7CH 73H 74H 75H 76H 77H 7BH 79H 7AH 7DH 7FH 7EH Sector 1 Sector 0 Sector 1 Sector 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 0...

Page 32: ...g to the registers will result in no operation Memory Pointers MP0 MP1L MP1H MP2L MP2H Five Memory Pointers known as MP0 MP1L MP1H MP2L MP2H are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing ...

Page 33: ...data to acc lsub a m 1 compare m and m 1 data snz c m m 1 jmp continue no lmov a m yes exchange m and m 1 data mov temp a lmov a m 1 lmov m a mov a temp lmov m 1 a continue Note here m is a data memory address located in any data memory sectors For example m 1F0H it indicates address 0F0H in Sector 1 Accumulator ACC The Accumulator is central to the operation of any microcontroller and is closely ...

Page 34: ...d the status and operation of the microcontroller With the exception of the TO and PDF flags bits in the status register can be altered by instructions like most other registers Any data written into the status register will not change the TO or PDF flag In addition operations related to the status register may give different results due to the different instruction operations The TO flag can be a...

Page 35: ...he previous operation CZ flag and current operation zero flag For other instructions the CZ flag will not be affected Bit 5 TO Watchdog Time out flag 0 After power up or executing the CLR WDT or HALT instruction 1 A watchdog time out occurred Bit 4 PDF Power down flag 0 After power up or executing the CLR WDT instruction 1 By executing the HALT instruction Bit 3 OV Overflow flag 0 No overflow 1 An...

Page 36: ... in Sector 0 and a single control register in Sector 1 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control register EEC As both the EEA and EED registers are located in Sector 0 they can be directly accessed in the same was as any other Special Function Register The EEC regis...

Page 37: ...is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle This bit will be automatically reset to zero by the hardware after the read cycle has finished Setting this bit high will have no effect if the RDEN has not first been set high Note 1 The WREN WR RDEN and RD cannot be set high at the same time in one instruction The WR and RD cannot be set h...

Page 38: ... Data Memory Sector 0 will be selected As the EEPROM control register is located in Sector 1 this adds a further measure of protection against spurious write operations During normal program operation ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write c...

Page 39: ...required CLR MP1H MOV A EED move read data to register MOV READ_DATA A Note For each read operation the address register should be re specified followed by setting the RD bit high to activate a read cycle even if the target address is consecutive Writing Data to the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A EEPROM_DATA user defined data MOV EED A MOV A 040H setu...

Page 40: ...quency oscillator With the capability of dynamically switching between fast and slow system clock the device has the flexibility to optimise the performance power ratio a feature especially important in power sensitive portable applications Type Name Frequency Internal High Speed RC HIRC 8 12 16MHz Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods ...

Page 41: ...y applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks required for high performance will by their nature increase current consumption and of course vice versa lower speed clocks reduce current consumption ...

Page 42: ... its own special characteristics and which can be chosen according to the specific performance and power requirements of the application There are two modes allowing normal operation of the microcontroller the FAST Mode and SLOW Mode The remaining four modes the SLEEP IDLE0 IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power Operation Mode CPU Register Sett...

Page 43: ...clock can continues to operate if the WDT function is enabled IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some peripheral functions IDLE1 Mode The IDLE1 Mode is entered w...

Page 44: ...sed to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an HALT instruction HIRCC Register Bit 7 6 5 4 3 2 1 0 Name HIRC1 HIRC0 HIRCF HIRCEN R W R W R W R R W POR 0 0 0 1 Bit 7 4 Unimplemented read as 0 Bit 3 2 HIRC1 HIRC0 HIRC frequency selection 00 8MHz 01 12MHz 10 16MHz 11 8MHz When the HIRC oscillator is enabled or the HIRC frequency se...

Page 45: ... condition of the FHIDEN and FSIDEN bits in the SCC register FAST fSYS fH fH 64 fH on CPU run fSYS on fSUB on SLOW fSYS fSUB fSUB on CPU run fSYS on fH on off IDLE0 HALT instruction executed CPU stop FHIDEN 0 FSIDEN 1 fH off fSUB on IDLE1 HALT instruction executed CPU stop FHIDEN 1 FSIDEN 1 fH on fSUB on IDLE2 HALT instruction executed CPU stop FHIDEN 1 FSIDEN 0 fH on fSUB off SLEEP HALT instructi...

Page 46: ...t to 000 110 and then the system clock will respectively be switched to fH fH 64 However if fH is not used in SLOW mode and thus switched off it will take some time to re oscillate and stabilise when switching to the FAST mode from the SLOW Mode This is monitored using the HIRCF bit in the HIRCC register The time duration required for the high speed system oscillator stabilization is specified in ...

Page 47: ...T instruction but the fSUB clock will be on The Data Memory contents and registers will maintain their present condition The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and the Watchdog time out flag TO will be cleared The WDT will be cleared and resume counting if the WDT function is enabled If the WDT function is disabled the WDT wi...

Page 48: ...ly to external circuits that do not draw current such as other CMOS inputs Also note that additional standby current will also be required if the LIRC oscillator has enabled In the IDLE1 and IDLE2 Mode the high speed oscillator is on if the peripheral function clock source is derived from the high speed oscillator the additional standby current will also be perhaps in the order of several hundred ...

Page 49: ...oscillator The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with VDD temperature and process variations The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts the actual value being chosen using the WS2 WS0 bits in the WDTC register Watchdog Timer Control Register A single register WDTC ...

Page 50: ...he WDT function will be disabled when the WE4 WE0 bits are set to a value of 10101B while the WDT function will be enabled if the WE4 WE0 bits are equal to 01010B If the WE4 WE0 bits are set to any other values other than 01010B and 10101B it will reset the device after a delay time tSRESET After power on these bits will have a value of 01010B WE4 WE0 Bits WDT Function 10101B Disable 01010B Enable...

Page 51: ...s in the form of a Low Voltage Reset LVR where a full reset is implemented in situations where the power supply voltage falls below a certain threshold Another type of reset is when the Watchdog Timer overflows and resets the microcontroller All types of reset operations result in different register conditions being setup Reset Functions There are several ways in which a microcontroller reset can ...

Page 52: ...SLEEP or IDLE mode LVR Internal Reset tRSTD tSST Low Voltage Reset Timing Chart LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 1 0 1 Bit 7 0 LVS7 LVS0 LVR Voltage Select control 01010101 2 1V 00110011 2 55V 10011001 3 15V 10101010 3 8V Any other value Generates MCU reset register is reset to POR value When an actual ...

Page 53: ... out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1 Refer to the System Start Up Time Characteristics for tSST details WDT Time out Internal Reset tSST WDT Time out Reset during SLEEP or IDLE Timing Chart Reset Initial ...

Page 54: ...ACC x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBLP x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u TBLH x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u TBHP x x x x u u u u u u u u u u u u STATUS x x 0 0 x x x x u u u u u u u u u u 1 u u u u u u u 11 u u u u IAR2 0 0 0 0 0 0 0 ...

Page 55: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u STMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u STMDL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u STMDH 0 0 0 0 0 0 u u STMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u STMAH 0 0 0 0 0 0 u u PTMC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u PTMC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 56: ... 0 u u u u u u u u IFS2 0 0 0 0 0 0 0 0 0 0 0 0 u u u u PAS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PAS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PDS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PDS1 0 0 0 0 0 0 0 0 0 0 0 0 u u u u CTMC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTMC1 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 57: ...PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PD PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 Unimplemented read as 0 I O Logic Function Register List Pull high Resistors Many product applications require pull high resistors for their switch inputs usually requiring the use of an external resisto...

Page 58: ...ynamically under software control Each pin of the I O ports is directly mapped to a bit in its associated port control register For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then allow the logic state of the input pin to be directly read by instructions When the corresponding bit of the control register is written as a 0 the ...

Page 59: ...device can contain However by allowing the same pins to share several different functions and providing a means of function selection a wide range of different functions can be incorporated into even relatively small package sizes The device includes Port x Output Function Selection register n labeled as PxSn and Input Function Selection register i labeled as IFSi which can select the desired func...

Page 60: ...S07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00 IFS1 IFS17 IFS16 IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS2 IFS23 IFS22 IFS21 IFS20 Pin shared Function Selection Register List PAS0 Register Bit 7 6 5 4 3 2 1 0 Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PAS07 PAS06 PA3 Pin Shared function selection 00 PA3 INT1 PTPI 01 OVPI1 10 SC...

Page 61: ... 5 4 PAS15 PAS14 PA6 Pin Shared function selection 00 PA6 INT1 01 SDI SDA RX 10 STP 11 AN6 Bit 3 2 PAS13 PAS12 PA5 Pin Shared function selection 00 PA5 INT0 01 SCK SCL 10 STPB 11 AN5 Bit 1 0 PAS11 PAS10 PA4 Pin Shared function selection 00 PA4 CTCK STCK PTCK 01 SDI SDA RX 10 VREF 11 AN4 PBS1 Register Bit 7 6 5 4 3 2 1 0 Name PBS13 PBS12 R W R W R W POR 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 P...

Page 62: ... STP 10 PC0 11 PC0 PDS0 Register Bit 7 6 5 4 3 2 1 0 Name PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PDS07 PDS06 PD3 Pin Shared function selection 00 PD3 CTCK 01 OVPINT 10 PD3 CTCK 11 PD3 CTCK Bit 5 4 PDS05 PDS04 PD2 Pin Shared function selection 00 PD2 01 CTP 10 PD2 11 PD2 Bit 3 2 PDS03 PDS02 PD1 Pin Shared function selection 00...

Page 63: ...nction selection 00 PD4 01 CTPB 10 PTPB 11 PD4 IFS0 Register Bit 7 6 5 4 3 2 1 0 Name IFS07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 IFS07 IFS06 PTCK input source pin selection 00 PD1 01 PD1 10 PA4 11 PA4 Bit 5 4 IFS05 IFS04 SDI SDA RX input source pin selection 00 PA2 01 PA2 10 PA6 11 PA4 Bit 3 2 IFS03 IFS02 SCK SCL input source pin...

Page 64: ...4 STPI input source pin selection 00 PA1 01 PA1 10 PD0 11 PD0 Bit 3 2 IFS13 IFS12 INT1 input source pin selection 00 PA3 01 PA3 10 PA6 11 PA6 Bit 1 0 IFS11 IFS10 INT0 input source pin selection 00 PA1 01 PA1 10 PA5 11 PA5 IFS2 Register Bit 7 6 5 4 3 2 1 0 Name IFS23 IFS22 IFS21 IFS20 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 IFS23 IFS22 CTCK input source pin selection...

Page 65: ...to an input state the level of which depends on the other connected circuitry and whether pull high selections have been chosen If the port control registers are then programmed to setup some pins as outputs these output pins will have an initial high output value unless the associated port data registers are first programmed Selecting which pins are inputs and which are outputs can be achieved by...

Page 66: ...ferences between the three TM types are summarised in the accompanying table Function CTM STM PTM Timer Counter Input Capture Compare Match Output PWM Output Single Pulse Output PWM Alignment Edge Edge Edge PWM Adjustment Period Duty Duty or Period Duty or Period Duty or Period TM Function Summary CTM STM PTM 10 bit CTM 10 bit STM 10 bit PTM TM Name Type Reference TM Operation The different types ...

Page 67: ...alling edges The active edge transition type is selected using the xTIO1 xTIO0 bits in the xTMC1 register For the PTM there is another capture input PTCK for PTM capture input mode which can be used as the external trigger input source except for the PTPI pin The TMs each has two output pins named xTP and xTPB The xTPB pin outputs the inverted signal of the xTP When the TM is in the Compare Match ...

Page 68: ...byte only takes place when a write or read operation to its corresponding high byte is executed As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above it is recommended to use the MOV instruction to access the CCRA and CCRP low byte registers named xTMAL and PTMRPL using the fol...

Page 69: ... 0 1 Output Control Polarity Control Pin Control CTOC CTM1 CTM0 CTIO1 CTIO0 CTMAF Interrupt CTMPF Interrupt CTPOL CCRA CTCCLR PxSn fSUB CTPB CTP CTCK PxSn IFSi Pin Control Note CTPB is the inverse signal of CTP Compact Type TM Block Diagram Compact Type TM Operation At its core is a 10 bit count up counter which is driven by a user selectable internal or external clock source There are also two in...

Page 70: ...n When in a Pause condition the CTM will remain powered up and continue to consume power The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again Bit 6 4 CTCK2 CTCK0 Select CTM Counter clock 000 fSYS 4 001 fSYS 010 fH 16 011 fH 64 100 fSUB 101 fSUB 110 CTCK rising edge clock 111 CTCK falling edge...

Page 71: ...ultiples Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value CTMC1 Register Bit 7 6 5 4 3 2 1 0 Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 CTM1 CTM0 Select CTM Operating Mode 00 Compare Match Output Mode 01 Undefined 10 PWM Output Mode 11 Timer Counter Mode These bits setup the re...

Page 72: ... upon whether CTM is being used in the Compare Match Output Mode or in the PWM Output Mode It has no effect if the CTM is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the CTM output pin before a compare match occurs In the PWM Output Mode it determines if the PWM signal is active high or active low Bit 2 CTPOL CTM CTP Output polarity Control 0 Non inv...

Page 73: ...R POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 CTM Counter High Byte Register bit 1 bit 0 CTM 10 bit Counter bit 9 bit 8 CTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 CTM CCRA Low Byte Register bit 7 bit 0 CTM 10 bit CCRA bit 7 bit 0 CTMAH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R W R W POR 0 0 Bit...

Page 74: ...re only the CTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when CTCCLR is high no CTMPF interrupt request flag will be generated If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the CTMAF interrupt request flag will not be generated As the name ...

Page 75: ... if CTOC 0 Output Toggle with CTMAF flag Note CTIO 1 0 10 Active High Output select Here CTIO 1 0 11 Toggle Output select Output not affected by CTMAF flag Remains High until reset by CTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTPOL is high Compare Match Output Mode CTCCLR 0 Note 1 With CTCCLR 0 a Comparator P match will clear the ...

Page 76: ...tput not affected by CTMAF flag Remains High until reset by CTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTPOL is high CTMPF not generated No CTMAF flag generated on CCRA overflow Output does not change CTCCLR 1 CTM 1 0 00 CCRA Int Flag CTMAF CCRP Int Flag CTMPF Compare Match Output Mode CTCCLR 1 Note 1 With CTCCLR 1 a Comparator A m...

Page 77: ...isters are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values i...

Page 78: ... Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRP CTM O P Pin CTOC 0 CCRA Int Flag CTMAF CCRP Int Flag CTMPF CTDPX 0 CTM 1 0 10 PWM Output Mode CTDPX 0 Note 1 Here CTDPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues running even when CTIO 1 0 00 or 01 4 The C...

Page 79: ...ounter Reset when CTON returns high PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRA CTM O P Pin CTOC 0 CTDPX 1 CTM 1 0 10 PWM Output Mode CTDPX 1 Note 1 Here CTDPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even when CTIO 1 0 00 or 01 4 The CTCCL...

Page 80: ...parator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 3 bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits and therefore compares all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changin...

Page 81: ... 16 011 fH 64 100 fSUB 101 fSUB 110 STCK rising edge clock 111 STCK falling edge clock These three bits are used to select the clock source for the STM The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the oscillator section Bit 3 STON STM ...

Page 82: ... STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 STM1 STM0 Select STM Operating Mode 00 Compare Match Output Mode 01 Capture Input Mode 10 PWM Output Mode or Single Pulse Output Mode 11 Timer Counter Mode These bits setup the required operating mode for the STM To ensure reliable operation the STM should be switched off before any changes ar...

Page 83: ...epends upon whether STM is being used in the Compare Match Output Mode or in the PWM Output Mode Single Pulse Output Mode It has no effect if the STM is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs In the PWM Output Mode it determines if the PWM signal is active high or active low In the Single Pulse Ou...

Page 84: ...R POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 STM Counter High Byte Register bit 1 bit 0 STM 10 bit Counter bit 9 bit 8 STMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 STM CCRA Low Byte Register bit 7 bit 0 STM 10 bit CCRA bit 7 bit 0 STMAH Register Bit 7 6 5 4 3 2 1 0 Name D9 D8 R W R W R W POR 0 0 Bit...

Page 85: ...y the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when STCCLR is high no STMPF interrupt request flag will be generated In the Compare Match Output Mode the CCRA cannot be cleared to 0 If the CCRA bits are all zero the counter will overflow when it reaches its maximum 3FF Hex value however here the STMAF interr...

Page 86: ...TOC 0 Output Toggle with STMAF flag Note STIO 1 0 10 Active High Output select Here STIO 1 0 11 Toggle Output select Output not affected by STMAF flag Remains High until reset by STON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when STPOL is high Compare Match Output Mode STCCLR 0 Note 1 With STCCLR 0 a Comparator P match will clear the count...

Page 87: ...Output select Here STIO 1 0 11 Toggle Output select Output not affected by STMAF flag Remains High until reset by STON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when STPOL is high STMPF not generated No STMAF flag generated on CCRA overflow Output does not change Compare Match Output Mode STCCLR 1 Note 1 With STCCLR 1 a Comparator A match w...

Page 88: ...riod Both of the CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register The PWM waveform frequency and duty cycle can there...

Page 89: ... Reset when STON returns high STDPX 0 STM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when STPOL 1 PWM Period set by CCRP STM O P Pin STOC 0 PWM Output Mode STDPX 0 Note 1 Here STDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when STIO 1 0 00 or 01 4 The...

Page 90: ...nter Reset when STON returns high STDPX 1 STM 1 0 10 PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when STPOL 1 PWM Period set by CCRA STM O P Pin STOC 0 PWM Output Mode STDPX 1 Note 1 Here STDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when STIO 1 0 00 or 01 4 The STC...

Page 91: ...te The generated pulse trailing edge will be generated when the STON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge In this way the CCRA value can be used to control the pulse wid...

Page 92: ...utput Inverts when STPOL 1 No CCRP Interrupts generated STM O P Pin STOC 0 STCK pin Software Trigger Cleared by CCRA match STCK pin Trigger Auto set by STCK pin Software Trigger Software Clear Software Trigger Software Trigger Single Pulse Output Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the STCK pin or by setting the STON bit high 4 A STCK pin active edge wil...

Page 93: ...events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a STM interrupt will also be generated Counting the number of overflow interrupt signals from...

Page 94: ...0 Value XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 STM 1 0 01 and active edge set by the STIO 1 0 bits 2 A STM Capture input pin active edge transfers the counter value to CCRA 3 STCCLR and STDPX bits not used 4 No output function STOC and STPOL bits are not used 5 CCRP determines the counter value and t...

Page 95: ...are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP and CCRA comparators are 10 bit wide whose value is compared with all counter bits The only way of changing the value of the 10 bit counter using the application program is to clear the counter by changing the PTON bit from low...

Page 96: ...1 fH 64 100 fSUB 101 fSUB 110 PTCK rising edge clock 111 PTCK falling edge clock These three bits are used to select the clock source for the PTM The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the oscillator section Bit 3 PTON PTM Counte...

Page 97: ...condition is reached The function that these bits select depends upon in which mode the PTM is running In the Compare Match Output Mode the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A The PTM output pin can be setup to switch high switch low or to toggle its present state when a compare match occurs from the Comparator A Whe...

Page 98: ... 1 PTCAPTS PTM Capture Trigger Source selection 0 From PTPI pin 1 From PTCK pin Bit 0 PTCCLR PTM Counter Clear condition selection 0 PTM Comparator P match 1 PTM Comparator A match This bit is used to select the method which clears the counter Remember that the Periodic Type TM contains two comparators Comparator A and Comparator P either of which can be selected to clear the internal counter With...

Page 99: ...t 7 2 Unimplemented read as 0 Bit 1 0 D9 D8 PTM CCRA High Byte Register bit 1 bit 0 PTM 10 bit CCRA bit 9 bit 8 PTMRPL Register Bit 7 6 5 4 3 2 1 0 Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PTRP7 PTRP0 PTM CCRP Low Byte Register bit 7 bit 0 PTM 10 bit CCRP bit 7 bit 0 PTMRPH Register Bit 7 6 5 4 3 2 1 0 Name PTRP9 PTRP8 R W...

Page 100: ...e PTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when PTCCLR is high no PTMPF interrupt request flag will be generated In the Compare Match Output Mode the CCRA can not be cleared to 0 If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the PTMAF i...

Page 101: ... with PTMAF flag Note PTIO 1 0 10 Active High Output select Here PTIO 1 0 11 Toggle Output select Output not affected by PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTPOL is high PTCCLR 0 PTM 1 0 00 Compare Match Output Mode PTCCLR 0 Note 1 With PTCCLR 0 a Comparator P match will clear the coun...

Page 102: ...PTIO 1 0 11 Toggle Output select Output not affected by PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when PTPOL is high PTMPF not generated No PTMAF flag generated on CCRA overflow Output does not change PTCCLR 1 PTM 1 0 00 Compare Match Output Mode PTCCLR 1 Note 1 With PTCCLR 1 a Comparator A match ...

Page 103: ...oth the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM Output Mode the PTCCLR bit has no effect as the PWM period Both of the CCRP and CCRA registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control...

Page 104: ... low Counter Reset when PTON returns high PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts When PTPOL 1 PWM Period set by CCRP PTM O P Pin PTOC 0 PTM 1 0 10 PWM Output Mode Note 1 The counter is cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when PTIO 1 0 00 or 01 4 The PTCCLR bi...

Page 105: ...ulse leading edge will be generated The PTON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PTON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the PTON bit and thus generat...

Page 106: ...L 1 No CCRP Interrupts generated PTM O P Pin PTOC 0 PTCK pin Software Trigger Cleared by CCRA match PTCK pin Trigger Auto set by PTCK pin Software Trigger Software Clear Software Trigger Software Trigger PTM 1 0 10 PTIO 1 0 11 Single Pulse Output Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the PTCK pin or by setting the PTON bit high 4 A PTCK pin active edge wil...

Page 107: ...d Irrespective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a PTM interrupt will also be generated Counting the number of ...

Page 108: ...op PTIO 1 0 Value XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 PTM 1 0 01 and active edge set by the PTIO 1 0 bits 2 A PTM Capture input pin active edge transfers the counter value to CCRA 3 PTCCLR bit not used 4 No output function PTOC and PTPOL bits are not used 5 CCRP determines the counter value and th...

Page 109: ... shared with I O or other pin functions before turning on the OVP function make sure the OVP pin functions are selected using the corresponding Pin shared Function Selection Registers 2 The on off control for the switches S0 S1 and S2 is summarised below OVPCOFM OVPCRS S0 S1 S2 0 x ON ON OFF 1 0 OFF ON ON 1 1 ON OFF ON x Don t care Over Voltage Protection Registers Overall operation of the over vo...

Page 110: ...r of the OVP all being switched off Bit 4 3 Unimplemented read as 0 Bit 2 0 OVPDEB2 OVPDEB0 OVP comparator debounce time setup 000 No debounce 001 1 2 1 fSYS 010 3 4 1 fSYS 011 7 8 1 fSYS 100 15 16 1 fSYS 101 31 32 1 fSYS 110 63 64 1 fSYS 111 127 128 1 fSYS OVPC1 Register Bit 7 6 5 4 3 2 1 0 Name OVPCOUT OVPCOFM OVPCRS OVPCOF4 OVPCOF3 OVPCOF2 OVPCOF1 OVPCOF0 R W R R W R W R W R W R W R W R W POR 0...

Page 111: ...ollowing Step1 Set OVPCOFM 1 OVPCRS 1 the OVP is now in the comparator offset calibration mode S0 and S2 on To make sure VOS as minimise as possible after calibration the input reference voltage in calibration mode should be the same as input DC operating voltage in normal mode operation Step2 Set OVPCOF 4 0 00000 and then read the OVPCOUT bit status after a certain delay Step3 Increase the OVPCOF...

Page 112: ...erated by the internal A D Converter input channel selection When the A D Converter selects the VCC1O signal as its internal input then CWSEL 0 otherwise CWSEL 1 LDO Block Diagram High Voltage I O Ports The device provides several 12V high voltage input output lines known as PB0 PB7 PC0 and PC1 These high voltage I O ports can convert 5V logic output signals to 12V voltage outputs to directly driv...

Page 113: ...ls information about PB5 CTP PC0 STP and PC1 PTP refer to the Pin shared Functions section 5 When the comparison result between Pxn_DOUT and Pxn_DIN is different the LIRC oscillator will be enabled by the hardware until the short circuit condition is released even if the CPU and LIRC are both off After the LIRC clock is stable the fLIRC can be used as the clock source of the peripheral functions I...

Page 114: ...BOM2 PBOM1 PBOM0 PC PC1 PC0 PCC PCC1 PCC0 PCOM PCOM1 PCOM0 PBMOSC0 PBMOSC07 PBMOSC06 PBMOSC05 PBMOSC04 PBMOSC03 PBMOSC02 PBMOSC01 PBMOSC00 PBMOSC1 PBMOSC17 PBMOSC16 PBMOSC15 PBMOSC14 PBMOSC13 PBMOSC12 PBMOSC11 PBMOSC10 PCMOSC0 PCMOSC03 PCMOSC02 PCMOSC01 PCMOSC00 PWRDET PWRRDYF SFRTC High Voltage I O Register List PB Register Bit 7 6 5 4 3 2 1 0 Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 R W R W R W R W ...

Page 115: ...ister Bit 7 6 5 4 3 2 1 0 Name PCOM1 PCOM0 R W R W R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 PCOM1 PCOM0 HVIO PC1 PC0 output mask control 0 No output mask 1 Output mask PBMOSC0 Register Bit 7 6 5 4 3 2 1 0 Name PBMOSC07 PBMOSC06 PBMOSC05 PBMOSC04 PBMOSC03 PBMOSC02 PBMOSC01 PBMOSC00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PBMOSC07 PBMOSC06 PB3 output control 00 CMO...

Page 116: ...MOSC14 PB6 output control 00 CMOS output 01 NMOS output 10 PMOS output 11 Output is disabled Bit 3 2 PBMOSC13 PBMOSC12 PB5 output control 00 CMOS output 01 NMOS output 10 PMOS output 11 Output is disabled Bit 1 0 PBMOSC11 PBMOSC10 PB4 output control 00 CMOS output 01 NMOS output 10 PMOS output 11 Output is disabled PCMOSC0 Register Bit 7 6 5 4 3 2 1 0 Name PCMOSC03 PCMOSC02 PCMOSC01 PCMOSC00 R W R...

Page 117: ...IRC 1 2 3 8 tLIRC Voltage Detector An internal voltage detector circuit is used to monitor the VCC2 and VDD voltage levels It provides a power ready flag PWRRDYF which can be read by the MCU to indicate the power status If the VCC2 is equal to or greater than the VDET1 and the VDD is equal to or greater than the VDET2 then PWRRDYF 1 otherwise PWRRDYF 0 In addition there is also a VCC2O voltage out...

Page 118: ...ter the short circuit condition occurs the high voltage short circuit interrupt flag HVSCF will be set high The short circuit protection circuit use the same interrupt vector for all high voltage I O The short circuit condition will trigger an high voltage short circuit interrupt irrespective of which high voltage I O occurs When this condition appears if the global interrupt enable bit and its co...

Page 119: ...al data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices The communication is full duplex and operates as a slave master type where the device can be either master or slave Although the SPI interface specification can control multiple slave devices from a single master but the device provides on...

Page 120: ...ernal registers which control the overall operation of the SPI interface These are the SIMD data register and two control registers SIMC0 and SIMC2 Note that the SIMC2 and SIMD registers and their POR values are only available when the SPI mode is selected by properly configuring the UMD and SIM2 SIM0 bits in the SIMC0 register Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 UMD SIMDEB1 SIM...

Page 121: ...s well as selecting if the I2 C or SPI function they are used to control the SPI Master Slave selection and the SPI Master clock frequency The SPI clock is a function of the system clock but can also be chosen to be sourced from PTM and fSUB If the SPI Slave Mode is selected then the clock will be supplied by an external Master device Bit 4 UMD UART mode selection bit 0 SPI or I2 C mode 1 UART mod...

Page 122: ... W POR 0 0 0 0 0 0 0 0 Bit 7 6 D7 D6 Undefined bits These bits can be read or written by the application program Bit 5 CKPOLB SPI clock line base condition selection 0 The SCK line will be high when the clock is inactive 1 The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line if the bit is high then the SCK line will be low when the cloc...

Page 123: ...he SIMEN bit high then in the Master Mode when data is written to the SIMD register transmission reception will begin simultaneously When the data transfer is completed the TRF flag will be set high automatically but must be cleared using the application program In the Slave Mode when the clock signal from the master has been received any data in the SIMD register will be transmitted and any data ...

Page 124: ...D7 D0 D6 D1 D5 D2 D4 D3 D3 D4 D2 D5 D1 D6 D0 D7 SPI Slave Mode Timing CKEG 0 SCK CKPOLB 1 SCK CKPOLB 0 SCS SDO SDI Data Capture D7 D0 D6 D1 D5 D2 D4 D3 D3 D4 D2 D5 D1 D6 D0 D7 Write to SIMD SDO changes as soon as writing occurs SDO is floating if SCS 1 Note For SPI slave mode if SIMEN 1 and CSEN 0 SPI is always enabled and ignores the SCS level SPI Slave Mode Timing CKEG 1 ...

Page 125: ...ld be set For the Slave Mode when clock pulses are received on SCK data in the TXRX buffer will be shifted out and data on SDI will be shifted in When the SPI bus is disabled SCK SDI SDO and SCS can become I O pins or other pin shared functions using the corresponding pin shared control bits SPI Operation Steps All communication is carried out using the 4 line interface for either Master or Slave ...

Page 126: ...e same with the Slave devices Step 3 Setup the SIMEN bit in the SIMC0 control register to enable the SPI interface Step 4 For write operations write the data to the SIMD register which will actually place the data into the TXRX buffer Then use the SCK and SCS lines to output the data After this go to step 5 For read operations the data transferred in on the SDI line will be stored in the TXRX buff...

Page 127: ...lines for communication relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications Device Slave Device Master Device Slave VDD SDA SCL I2 C Master Slave Bus Connection I2 C Interface Operation The I2 C serial interface is a two line interface a serial data line SDA and serial clock l...

Page 128: ...ation The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2 C interface This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation The debounce time if selected can be chosen to be either 2 or 4 system clocks To achieve the required I2 C data transfer speed there exists a relat...

Page 129: ...r Any transmission or reception of data from the I2 C bus must be made via the SIMD register SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR x x x x x x x x x unknown Bit 7 0 D7 D0 USIM SPI I2 C data register bit 7 bit 0 I2 C Address Register The SIMA register is also used by the SPI interface but has the name SIMC2 The SIMA register is the lo...

Page 130: ...can be selected using the SIM2 SIM0 bits Note that the UMD bit must be cleared to zero for SPI or I2 C mode Bit 3 2 SIMDEB1 SIMDEB0 I2 C Debounce Time Selection 00 Undefined 01 2 system clock debounce 1x 4 system clock debounce These bits are used to select the I2 C debounce time when the USIM is configured as the I2 C interface function by clearing the UMD bit to 0 and the SIM2 SIM0 bits to 110 B...

Page 131: ...ave device is the receiver 1 Slave device is the transmitter Bit 3 TXAK I2 C Bus transmit acknowledge flag 0 Slave send acknowledge flag 1 Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag After the slave device receipt of 8 bits of data this bit will be transmitted to the bus on the 9th clock from the slave device The slave device must always set TXAK bit to 0 befor...

Page 132: ...hes that of the transmitted address the HAAS bit in the SIMC1 register will be set and an USIM interrupt will be generated After entering the interrupt service routine the slave device must first check the condition of the HAAS and SIMTOF bits to determine whether the interrupt source originates from an address match or from the completion of an 8 bit data transfer completion or from the I2 C bus ...

Page 133: ... to release the SCL line I2 C Bus Read Write Signal The SRW bit in the SIMC1 register defines whether the master device wishes to read data from the I2 C bus or write data to the I2 C bus The slave device should examine this bit to determine if it is to be a transmitter or a receiver If the SRW flag is 1 then this indicates that the master device wishes to read data from the I2 C bus therefore the...

Page 134: ...it in the SIMC1 register to determine if it is to send another data byte if not then it will release the SDA line and await the receipt of a STOP signal from the master Start SCL SDA SCL SDA 1 S Start 1 bit SA Slave Address 7 bits SR SRW bit 1 bit M Slave device send acknowledge bit 1 bit D Data 8 bits A ACK RXAK bit for transmitter TXAK bit for receiver 1 bit P Stop 1 bit 0 ACK Slave Address SRW ...

Page 135: ...SR Flow Chart I2 C Time out Control In order to reduce the problem of I2 C lockup due to reception of erroneous clock sources a time out function is provided If the clock source to the I2 C is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts counting on an I2 C bus START address match condition and is cleared b...

Page 136: ... SIMD SIMA SIMC0 No change SIMC1 Reset to POR condition I2 C Registers after Time out The SIMTOF flag can be cleared by the application program There are 64 time out periods which can be selected using SIMTOS bit field in the SIMTOC register The time out time is given by the formula 1 64 32 fSUB This gives a time out period which ranges from about 1ms to 64ms SIMTOC Register Bit 7 6 5 4 3 2 1 0 Na...

Page 137: ...ort for interrupt on address detect last character bit 1 Separately enabled transmitter and receiver 2 byte Deep FIFO Receive Data Buffer RX pin wake up function Transmit and receive interrupts Interrupts can be triggered by the following conditions Transmitter Empty Transmitter Idle Receiver Full Receiver Overrun Address Mode Detect MSB LSB Transmitter Shift Register TSR MSB LSB Receiver Shift Re...

Page 138: ...is therefore inaccessible to the application program It should be noted that the actual register for data transmission and reception only exists as a single shared register in the Data Memory This shared register known as the UTXR_RXR register is used for both data transmission and data reception UART Status and Control Registers There are six control registers associated with the UART function Th...

Page 139: ...flag is the parity error flag When this read only flag is 0 it indicates a parity error has not been detected When the flag is 1 it indicates that the parity of the received word is incorrect This error flag is applicable only if Parity mode odd or even is selected The flag can also be cleared by a software sequence which involves a read to the status register UUSR followed by an access to the UTX...

Page 140: ...ed if URIE 1 in the UUCR2 register If one or more errors are detected in the received word the appropriate receive related flags UNF UFERR and or UPERR are set within the same clock cycle The URXIF flag will eventually be cleared when the UUSR register is read with URXIF set followed by a read from the UTXR_RXR register and if the UTXR_RXR register has no more new data available Bit 1 UTIDLE Trans...

Page 141: ...will be terminated and the module will be reset as defined above When the UART is re enabled it will restart in the same configuration Bit 6 UBNO Number of data transfer bits selection 0 8 bit data transfer 1 9 bit data transfer This bit is used to select the data length format which can have a choice of either 8 bit or 9 bit format When this bit is equal to 1 a 9 bit data length format will be se...

Page 142: ...rol 0 UART transmitter is disabled 1 UART transmitter is enabled The bit named UTXEN is the Transmitter Enable Bit When this bit is equal to 0 the transmitter will be disabled with any pending data transmissions being aborted In addition the buffers will be reset In this situation the TX pin will be set in a floating state If the UTXEN bit is equal to 1 and the UMD and UREN bit are also equal to 1...

Page 143: ...enabled an RX pin wake up UART interrupt will be generated to inform the MCU to wake up the UART function by switching on the UART clock fH via the application program Otherwise the UART function cannot resume even if there is a falling edge on the RX pin when the UWAKE bit is cleared to 0 Bit 2 URIE Receiver interrupt enable control 0 Receiver related interrupt is disabled 1 Receiver related inte...

Page 144: ...the second is the value of the UBRGH bit with the control register UUCR2 The UBRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode which in turn determines the formula that is used to calculate the baud rate The value N in the UBRG register which is used in the following baud rate calculation formula determines the division factor Note that N is the deci...

Page 145: ...bit will disable the TX and RX pins and allow these two pins to be used as normal I O or other pin shared functional pins by configuring the corresponding pin shared control bits When the UART function is disabled the buffer will be reset to an empty condition at the same time discarding any remaining residual data Disabling the UART will also reset the error and status flags with bits UTXEN URXEN...

Page 146: ...ailable It should be noted that the TSR register unlike many other registers is not directly mapped into the Data Memory area and as such is not available to the application program for direct read write operations An actual transmission of data will normally be enabled when the UTXEN bit is set but the data will not be transmitted until the UTXR_RXR register has been loaded with data and the baud...

Page 147: ...he UTXBRK bit is set then break characters will be sent on the next transmission Break character transmission consists of a start bit followed by 13 N 0 bits and stop bits where N 1 2 etc If a break character is to be transmitted then the UTXBRK bit must be first set by the application program and then cleared to generate the stop bits Transmitting a break character will not generate a transmit in...

Page 148: ...XR_RXR register read execution Receive Break Any break character received by the UART will be managed as a framing error The receiver will count and expect a certain number of bit times as specified by the values programmed into the UBNO bit plus one stop bit If the break is much longer than 13 bit times the reception will be considered as complete after the number of bit times specified by UBNO p...

Page 149: ...R_RXR register Noise Error UNF Over sampling is used for data recovery to identify valid incoming data and noise If noise is detected within a frame the following will occur The read only noise flag UNF in the UUSR register will be set on the rising edge of the URXIF bit Data will be transferred from the Shift register to the UTXR_RXR register No interrupt will be generated However this bit rises ...

Page 150: ...ting the UADDEN bit in the UUCR2 register An RX pin wake up which is also an USIM UART mode interrupt source does not have an associated flag but will generate an USIM interrupt if the UART clock fH source is switched off and the UWAKE and URIE bits in the UUCR2 register are set when a falling edge on the RX pin occurs Note that in the event of an RX wake up interrupt occurring there will be a cer...

Page 151: ...hutdown If the UART clock fH is off while a transmission is still in progress then the transmission will be paused until the UART clock source derived from the microcontroller is activated In a similar way if the MCU enters the IDLE or SLEEP Mode while receiving data then the reception of data will likewise be paused When the MCU enters the IDLE or SLEEP Mode note that the UUSR UUCR1 UUCR2 transmi...

Page 152: ... a 12 bit digital value The external or internal analog signal to be converted is determined by the SAINS2 SAINS0 bits together with the SACS3 SACS0 bits When the external analog signal is to be converted the corresponding pin shared control bits should first be properly configured and then desired external channel input should be selected using the SAINS2 SAINS0 and SACS3 SACS0 bits Note that whe...

Page 153: ... keep unchanged if the A D Converter is disabled ADRFS SADOH SADOL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A D Converter Data Registers A D Converter Control Registers SADC0 SADC1 To control the function and operation of the A D Converter two control registers known as SADC0 and SADC1 are provided These 8 bit r...

Page 154: ...EN A D Converter function enable control 0 Disable 1 Enable This bit controls the A D Converter internal function This bit should be set high to enable the A D Converter If the bit is cleared to zero then the A D Converter will be switched off reducing the device power consumption When the A D Converter function is disabled the contents of the A D Converter data register pair SADOH and SADOL will ...

Page 155: ...s the reference voltage source When the internal A D Converter power is selected as the reference voltage the VREF pin cannot be configured as the reference voltage input by properly configuring the corresponding pin shared function control bits Otherwise the external input voltage on VREF pin will be connected to the internal A D Converter power Bit 2 0 SACKS2 SACKS0 A D conversion clock source s...

Page 156: ...xternal channel is selected If the internal analog signal is selected to be converted the SACS3 SACS0 bits must be configured with a value from 1000 to 1111 to switch off the external analog channel input Otherwise the internal analog signal will be connected together with the external channel input This will result in unpredictable situations SAINS 2 0 SACS 3 0 Input Signals Description 000 101 1...

Page 157: ...667ns 1 33μs 2 67μs 5 33μs 10 67μs 16MHz 62 5ns 125ns 250ns 500ns 1μs 2μs 4μs 8μs A D Clock Period Examples Controlling the power on off function of the A D Converter circuitry is implemented using the ADCEN bit in the SADC0 register This bit must be set high to power on the A D Converter When the ADCEN bit is set high to power on the A D Converter internal circuitry a certain delay as indicated i...

Page 158: ...ted go to Step 5 Step 4 If the A D input signal comes from the external channel input selecting by configuring the SAINS bit field the corresponding pins should be configured as A D input function by configuring the relevant pin shared function control bits The desired analog channel then should be selected by configuring the SACS bit field After this step go to Step 6 Step 5 Before the A D input ...

Page 159: ...are must be taken as if the input voltage is not at a valid logic level then this may lead to some increase in power consumption A D Conversion Function As the device contains a 12 bit A D Converter its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to the actual A D Converter reference voltage VREF this gives a single bit analog input value ...

Page 160: ...l the SADC0 register ADBZ bit to detect end of A D conversion jmp polling_EOC continue polling mov a SADOL read low byte conversion result value mov SADOL_buffer a save result to user defined register mov a SADOH read high byte conversion result value mov SADOH_buffer a save result to user defined register jmp start_conversion start next A D conversion Example using the interrupt method to detect ...

Page 161: ...s register VLVD2 VLVD0 are used to select one of eight fixed voltages below which a low voltage condition will be determined A low voltage condition is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will e...

Page 162: ...r a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions VDD LVDEN LVDO VLVD tLVDS LVD Operation The Low Voltage Detector has its own interrupt providing an alternative means of low voltage detection in addition to p...

Page 163: ...se Data Memory as shown in the accompanying table The number of registers falls into three categories The first is the INTC0 INTC3 registers which setup the primary interrupts the second is the MFI register which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupts trigger edge type Each register contains a number of enable bits to enable or disab...

Page 164: ...isable 01 Rising edge 10 Falling edge 11 Rising and falling edges Bit 1 0 INT0S1 INT0S0 Interrupt edge control for INT0 pin 00 Disable 01 Rising edge 10 Falling edge 11 Rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Name USIMF OVPF INT0F USIME OVPE INT0E EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 USIMF USIM interrupt request flag 0 No req...

Page 165: ...h interrupt request flag 0 No request 1 Interrupt request Bit 3 STMAE STM Comparator A match interrupt control 0 Disable 1 Enable Bit 2 STMPE STM Comparator P match interrupt control 0 Disable 1 Enable Bit 1 PTMAE PTM Comparator A match interrupt control 0 Disable 1 Enable Bit 0 PTMPE PTM Comparator P match interrupt control 0 Disable 1 Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name TB0F ADF DEF L...

Page 166: ...t Bit 6 INT1F INT1 interrupt request flag 0 No request 1 Interrupt request Bit 5 HVSCF High Voltage Short Circuit interrupt request flag 0 No request 1 Interrupt request Bit 4 TB1F Time Base 1 interrupt request flag 0 No request 1 Interrupt request Bit 3 MFE Multi function interrupt control 0 Disable 1 Enable Bit 2 INT1E INT1 interrupt control 0 Disable 1 Enable Bit 1 HVSCE High Voltage Short Circ...

Page 167: ... interrupt service routine Here is located the code to control the appropriate interrupt The interrupt service routine must be terminated with a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred The various interrupt enable bits together with their associated request fl...

Page 168: ...e when the external interrupt request flags INT0F INT1F are set which will occur when a transition whose type is chosen by the edge select bits appears on the external interrupt pins To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and respective external interrupt enable bit INT0E INT1E must first be set Additionally the correct interru...

Page 169: ...d when a byte of data has been received or transmitted by the USIM SPI or I2 C interface or an I2 C slave address match occurs or an I2 C bus time out occurs If the UART mode is selected several individual UART conditions including a transmitter data register empty transmitter idle receiver data available receiver overrun address detect and an RX pin wake up can generate an USIM interrupt with the...

Page 170: ... place when the EEPROM Interrupt request flag DEF is set which occurs when an EEPROM Write cycle ends To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and EEPROM Interrupt enable bit DEE must first be set When the interrupt is enabled the stack is not full and an EEPROM Write cycle ends a subroutine call to the EEPROM Interrupt vector wi...

Page 171: ...EL1 CLKSEL0 Prescaler clock source selection 00 fSYS 01 fSYS 4 1x fSUB TB0C Register Bit 7 6 5 4 3 2 1 0 Name TB0ON TB02 TB01 TB00 R W R W R W R W R W POR 0 0 0 0 Bit 7 TB0ON Time Base 0 Control 0 Disable 1 Enable Bit 6 3 Unimplemented read as 0 Bit 2 0 TB02 TB00 Select Time Base 0 Time out Period 000 28 fPSC 001 29 fPSC 010 210 fPSC 011 211 fPSC 100 212 fPSC 101 213 fPSC 110 214 fPSC 111 215 fPSC...

Page 172: ...e interrupts contained within the Multi function interrupt occurs a subroutine call to the Multi function interrupt vector will take place When the interrupt is serviced the Multi Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts However it must be noted that although the Multi function Interrupt flag will be automatically r...

Page 173: ...is cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately If only one stack is left and the interrupt is not well controlled the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subrouti...

Page 174: ... HIRC Frequency Selection fHIRC 8MHz 12MHz or 16MHz Note When the HIRC has been configured at a frequency shown in this table the HIRC1 and HIRC0 bits should also be setup to select the same frequency to achieve the HIRC frequency accuracy specified in the A C Characteristics Application Circuits 10μF 0 1μF 5V 10μF 0 1μF R 10μF 0 1μF 12V VSS VDD VCC1 VCC2 1kΩ 100Ω 100μF Buzzer PC0 PC1 12V M 12V M ...

Page 175: ...o implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one cycle i...

Page 176: ...nstructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of cer...

Page 177: ... Carry result in Data Memory 1Note Z C AC OV SC CZ DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory...

Page 178: ... Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None ITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None ITABRDL m Increment table pointer TBLP first and Read ta...

Page 179: ... adjust ACC for Addition with result in Data Memory 2Note C Logic Operation LAND A m Logical AND Data Memory to ACC 2 Z LOR A m Logical OR Data Memory to ACC 2 Z LXOR A m Logical XOR Data Memory to ACC 2 Z LANDM A m Logical AND ACC to Data Memory 2Note Z LORM A m Logical OR ACC to Data Memory 2Note Z LXORM A m Logical XOR ACC to Data Memory 2Note Z LCPL m Complement Data Memory 2Note Z LCPLA m Com...

Page 180: ...sult in ACC 2Note None Table Read LTABRD m Read table to TBLH and Data Memory 3Note None LTABRDL m Read table last page to TBLH and Data Memory 3Note None LITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL m Increment table pointer TBLP first and Read table last page to TBLH and Data Memory 3Note None Miscellaneous LCLR m Clear Data Memory 2Note...

Page 181: ...tor and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C SC ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC AND A m Logical AND Data Memory to ACC Description ...

Page 182: ...eviously contained a 1 are changed to 0 and vice versa Operation m m Affected flag s Z CPLA m Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented 1 s complement Bits which previously contained a 1 are changed to 0 and vice versa The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged...

Page 183: ...tion m m 1 Affected flag s Z INCA m Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1 The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC m 1 Affected flag s Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address Program execut...

Page 184: ...g s Z RET Return from subroutine Description The Program Counter is restored from the stack Program execution continues at the restored address Operation Program Counter Stack Affected flag s None RET A x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data Program execution con...

Page 185: ... replaces the Carry bit and the original carry flag is rotated into the bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 C C m 7 Affected flag s C RR m Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7 Operation m i m i 1 ...

Page 186: ...C m C Affected flag s OV Z AC C SC CZ SBCM A m Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Data Memory Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive ...

Page 187: ... while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m 1 Skip if ACC 0 Affected flag s None SNZ m i Skip if Data Memory is not 0 Description If the specified Data Memory is not 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instructio...

Page 188: ...ry are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched...

Page 189: ...LH Operation m program code low byte TBLH program code high byte Affected flag s None ITABRDL m Increment table pointer low byte first and read table last page to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Op...

Page 190: ...d in the Accumulator Operation ACC ACC m Affected flag s OV Z AC C SC LADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC LAND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a ...

Page 191: ...he high nibble is greater than 9 or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by adding 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Ope...

Page 192: ...re rotated left by 1 bit with bit 7 rotated into bit 0 Operation m i 1 m i i 0 6 m 0 m 7 Affected flag s None LRLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 A...

Page 193: ...mory and the carry flag are rotated right by 1 bit Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 C C m 0 Affected flag s C LSBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and t...

Page 194: ...of the specified Data Memory is set to 1 Operation m i 1 Affected flag s None LSIZ m Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is not ...

Page 195: ...t to 1 Operation m ACC m Affected flag s OV Z AC C SC CZ LSWAP m Swap nibbles of Data Memory Description The low order and high order nibbles of the specified Data Memory are interchanged Operation m 3 m 0 m 7 m 4 Affected flag s None LSWAPA m Swap nibbles of Data Memory with result in ACC Description The low order and high order nibbles of the specified Data Memory are interchanged The result is ...

Page 196: ...ed flag s None LITABRD m Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the program code addressed by the table pointer TBHP and TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None LITABRDL m Increm...

Page 197: ...tervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Materials ...

Page 198: ...8 9 16 1 Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC D1 0 059 E2 0 039 C 0 012 0 020 C 0 390 BSC D 0 069 E 0 050 BSC F 0 000 0 006 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 00 BSC B 3 90 BSC D1 1 50 E2 1 00 C 0 31 0 51 C 9 90 BSC D 1 75 E 1 27 BSC F 0 00 0 15 G 0 40 1 27 H 0 10 0 25 α 0 8 ...

Page 199: ...mensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 D1 0 140 E 0 025 BSC E2 0 096 F 0 000 0 004 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions mm Min Nom Max A 6 00 BSC B 3 90 BSC C 0 20 0 30 C 8 66 BSC D 1 75 D1 3 56 E 0 635 BSC E2 2 44 F 0 00 0 10 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 200: ...ons Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 606 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 15 40 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 201: ...ons Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 705 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 17 90 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 202: ...ed solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reserve...

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