Holtek HT66F0175 Manual Download Page 22

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Rev. 1.50

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Rev. 1.50

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HT66F0175/HT66F0185

A/D Flash MCU with EEPROM

HT66F0175/HT66F0185

A/D Flash MCU with EEPROM

LVD/LVR Electrical Characteristics

Ta=�5°C

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

Conditions

LVR

Low Volta�e Reset Volta�e

—

LVR Enable� volta�e select �.1V

-5%

�.1

+5%

LVR Enable� volta�e select �.55V

�.55

LVR Enable� volta�e select 3.15V

3.15

LVR Enable� volta�e select 3.�V

3.�

LVD

Low Volta�e Detector Volta�e

—

LVD Enable� volta�e select �.0V

-5%

�.0

+5%

LVD Enable� volta�e select �.�V

�.�

LVD Enable� volta�e select �.4V

�.4

LVD Enable� volta�e select �.�V

�.�

LVD Enable� volta�e select 3.0V

3.0

LVD Enable� volta�e select 3.3V

3.3

LVD Enable� volta�e select 3.6V

3.6

LVD Enable� volta�e select 4.0V

4.0

Band�ap Reference Volta�e

—

-3% 1.04 +3%

Operatin� C�rrent

5V LVD/LVR Enable� VBGEN=0

—

�0

�5

μA

5V LVD/LVR Enable� VBGEN=1

—

1�0 �00

μA

BGS

T�rn on Stable Time

— No load

—

150

μs

LVDS

LVDO stable time

— For LVR enable� VBGEN=0�

LVD off

→

—

μs

— For LVR disable� VBGEN=0�

LVD off

→

—

150

μs

LVR

Minim�m Low Volta�e Width to Reset

—

1�0 �40 4�0

μs

LVD

Minim�m Low Volta�e Width to Interr�pt —

—

1�0 �40

μs

Comparator Electrical Characteristics

Ta=�5°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

Operatin� Volta�e

—

�.�

—

5.5

CMP

�dditional C�rrent Cons�mption

for comparator enable

—

3�

μA

—

130

�00

μA

Inp�t offset volta�e

—

-10

—

Common mode volta�e ran�e

—

-1.4

�

Open loop �ain

—

�0

—

HYS

Hysteresis

Hysteresis f�nction disabled

Hysteresis f�nction enabled

�0

Response time

— With 100mV overdrive

—

3�0

560

Summary of Contents for HT66F0175

Page 1: ...A D Flash MCU with EEPROM HT66F0175 HT66F0185 Revision V1 50 Date August 28 2017 ...

Page 2: ...istics 22 Software Controlled LCD Driver Electrical Characteristics 23 Power on Reset Characteristics 23 System Architecture 24 Clocking and Pipelining 24 Program Counter 25 Stack 26 Arithmetic and Logic Unit ALU 26 Flash Program Memory 27 Structure 27 Special Vectors 27 Look up Table 28 Table Program Example 28 In Circuit Programming ICP 29 On Chip Debug Support OCDS 30 Data Memory 31 Structure 3...

Page 3: ... Internal 32kHz Oscillator LIRC 44 Supplementary Oscillators 44 Operating Modes and System Clocks 45 System Clocks 45 System Operation Modes 46 Control Registers 47 Fast Wake up 49 Operating Mode Switching 50 Standby Current Considerations 54 Wake up 54 Programming Considerations 55 Watchdog Timer 55 Watchdog Timer Clock Source 55 Watchdog Timer Control Register 55 Watchdog Timer Operation 57 Rese...

Page 4: ...88 Standard Type TM Operation Modes 92 Periodic Type TM PTM 102 Periodic TM Operation 102 Periodic Type TM Register Description 103 Periodic Type TM Operation Modes 108 Analog to Digital Converter 117 A D Overview 117 A D Converter Register Description 118 A D Input Pins 124 A D Reference Voltage 124 A D Operation 124 Conversion Rate and Timing Diagram 125 Summary of A D Conversion Steps 126 Progr...

Page 5: ...164 UART Receiver 165 Managing Receiver Errors 167 UART Interrupt Structure 168 UART Power Down and Wake up 169 Low Voltage Detector LVD 170 LVD Register 170 LVD Operation 171 Interrupts 172 Interrupt Registers 172 Interrupt Operation 179 External Interrupt 181 Comparator Interrupt HT66F0185 181 Multi function Interrupt 181 A D Converter Interrupt 182 Time Base Interrupt 182 Serial Interface Modul...

Page 6: ... Control Transfer 188 Bit Operations 188 Table Read Operations 188 Other Operations 188 Instruction Set Summary 189 Table Conventions 189 Instruction Definition 191 Package Information 200 20 pin SOP 300mil Outline Dimensions 201 20 pin SSOP 150mil Outline Dimensions 202 24 pin SOP 300mil Outline Dimensions 203 24 pin SSOP 150mil Outline Dimensions 204 28 pin SOP 300mil Outline Dimensions 205 28 p...

Page 7: ... Memory Up to 128 8 Watchdog Timer function Up to 26 bidirectional I O lines Two external interrupt lines shared with I O pins Multiple Timer Modules for time measure input capture compare match output PWM output function or single pulse output function Serial Interfaces Module SIM for SPI or I2 C Software controlled 6 SCOM SSEG and 18 SSEG lines LCD driver with 1 3 bias Programmable I O port sour...

Page 8: ...for its implementation The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption The inclusion of flexible I O programming features Time Base functions along with many other features ensure that the devices will find excellent use in applications such as...

Page 9: ...D Converter RAM Data Memory SSEG SCOM UART Internal HIRC LIRC Oscillators For HT66F0185 For HT66F0185 Comparator Pin Assignment HT66F0175 HT66V0175 20 SOP A SSOP A 0 19 1 1 16 15 14 13 1 11 1 3 4 5 6 9 10 VSS VSS PC0 SSEG1 OSC1 PC1 SSEG1 OSC PC SDO SSEG0 SCOM0 P 0 TP0 ICPD OCDSD P ICPCK OCDSCK P 3 SDI SD SSEG3 SCOM3 PB6 SCK SCL SSEG4 SCOM4 P 1 SDO SCS SSEG SCOM PB5 SCS SSEG5 SCOM5 VDD VDD PB0 INT0...

Page 10: ...DSD P 1 SDO SSEG SCOM P ICPCK OCDSCK P 3 SDI SD CX SSEG3 SCOM3 PB6 SCK SCL C SSEG4 SCOM4 PB5 SCS C SSEG5 SCOM5 PC4 SDI SD SSEG PC5 SCK SCL SSEG1 SCOM1 HT66F0185 HT66V0185 28 SOP A SSOP A 6 5 4 3 1 0 19 1 1 16 15 1 3 4 5 6 9 10 11 1 13 14 VDD VDD PB0 INT0 SSEG1 N0 XT1 PB1 INT1 SSEG1 N1 XT PB TCK0 SSEG16 N P 4 TCK1 SSEG15 N3 P 5 SSEG10 N4 VREFI P 6 TCK SSEG9 N5 VREF P TP1 SSEG N6 PB3 TX TP SSEG N PB...

Page 11: ...S SPI data output SCS SLCDC0 SIMC0 IFS ST CMOS SPI slave select SSEG2 SLCDC0 SLCDC1 SSEG Software controlled LCD segment output SCOM2 SLCDC0 SLCDC1 SCOM Software controlled LCD common output PA2 ICPCK OCDSCK PA2 PAWU PAPU ST CMOS General purpose I O Register enabled pull up and wake up ICPCK ST CMOS ICP Clock pin OCDSCK ST OCDS Clock pin for EV chip only PA3 SDI SDA SSEG3 SCOM3 PA3 PAWU PAPU ST CM...

Page 12: ...urpose I O Register enabled pull up TCK0 TM0C0 ST TM0 input SSEG14 SLCDC3 SSEG Software controlled LCD segment output AN2 ACERL AN A D Converter analog input PB3 SSEG7 AN7 PB3 PBPU ST CMOS General purpose I O Register enabled pull up SSEG7 SLCDC2 SSEG Software controlled LCD segment output AN7 ACERL AN A D Converter analog input PB4 CLO SSEG6 PB4 PBPU ST CMOS General purpose I O Register enabled p...

Page 13: ... General purpose I O Register enabled pull up INT0 INTEG IFS ST External Interrupt 0 SSEG12 SLCDC2 SSEG Software controlled LCD segment output VDD AVDD VDD PWR Positive power supply AVDD PWR A D converter positive power supply VSS AVSS VSS PWR Negative power supply ground AVSS PWR A D converter negative power supply ground Note I T Input type O T Output type OPT Optional by configuration option CO...

Page 14: ... O Register enabled pull up and wake up TCK1 TM1C0 ST TM1 input SSEG15 SLCDC3 SSEG Software controlled LCD segment output AN3 ACERL AN A D Converter analog input PA5 SSEG10 AN4 VREFI PA5 PAWU PAPU ST CMOS General purpose I O Register enabled pull up and wake up SSEG10 SLCDC2 SSEG Software controlled LCD segment output AN4 ACERL AN A D Converter analog input VREFI SADC2 AN A D Converter PGA voltage...

Page 15: ...C2 SSEG Software controlled LCD segment output PB5 SCS C SSEG5 SCOM5 PB5 PBPU ST CMOS General purpose I O Register enabled pull up SCS SLCDC0 SIMC0 IFS ST CMOS SPI slave select C CPC AN Comparator input SSEG5 SLCDC1 SSEG Software controlled LCD segment output SCOM5 SLCDC1 SCOM Software controlled LCD common output PB6 SCK SCL C SSEG4 SCOM4 PB6 PBPU ST CMOS General purpose I O Register enabled pull...

Page 16: ...PDPU ST CMOS General purpose I O Register enabled pull up RX UCR1 UCR2 ST UART RX serial data input SSEG12 SLCDC2 SSEG Software controlled LCD segment output PD2 TX SSEG13 PD2 PDPU ST CMOS General purpose I O Register enabled pull up TX UCR1 UCR2 CMOS UART TX serial data output SSEG13 SLCDC2 SSEG Software controlled LCD segment output PD3 SSEG14 PD3 PDPU ST CMOS General purpose I O Register enable...

Page 17: ... Voltage HXT fSYS fHXT 8MHz 2 2 5 5 V fSYS fHXT 12MHz 2 7 5 5 V fSYS fHXT 16MHz 4 5 5 5 V fSYS fHXT 20MHz 4 5 5 5 V Operating Voltage HIRC fSYS fHIRC 8MHz 2 2 5 5 V fSYS fHIRC 12MHz 2 7 5 5 V fSYS fHIRC 16MHz 4 5 5 5 V IDD Operating Current HXT 3V fSYS fH fHXT 8MHz No load all peripherals off 1 0 1 5 mA 5V 2 5 4 0 mA 3V fSYS fH fHXT 12MHz No load all peripherals off 1 5 2 5 mA 5V 3 5 5 5 mA 5V fSY...

Page 18: ... 1 5 3 0 mA 5V fSYS fHIRC 16MHz on fSUB on No load all peripherals off 2 0 4 0 mA Standby Current SLEEP0 Mode 3V fSUB off WDT disable No load all peripherals off 1 0 μA 5V 2 0 μA Standby Current SLEEP1 Mode 3V fSUB on WDT enable No load all peripherals off 3 0 μA 5V 5 0 μA VIL Input Low Voltage for I O Ports or Input Pins 5V 0 1 5 V 0 0 2VDD V VIH Input High Voltage for I O Ports or Input Pins 5V ...

Page 19: ... 5 5V fSYS fLIRC 32kHz 32 kHz fLIRC Low Speed Internal RC oscillator LIRC 5V Ta 25 C 10 32 10 kHz 2 2V 5 5V Ta 40 C to 85 C 50 32 60 kHz tTCK TCKn pin Minimum Input Pulse Width 0 3 μs tINT Interrupt Pin Minimum Input Pulse Width 10 μs tSST System Start up Timer Period Wake up from power down mode and fSYS off fSYS fHXT off 128 tHXT fSYS fHIRC off 16 tHIRC fSYS fLXT off 128 tLXT fSYS fLIRC off 2 tL...

Page 20: ...trimmed 8MHz at VDD 5V Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions fHIRC High Speed Internal RC oscillator HIRC 5V Ta 25 C 2 8 2 MHz 5V 0 5V Ta 0 C 70 C 5 8 5 MHz 5V 0 5V Ta 40 C 85 C 7 8 7 MHz 2 2V 5 5V Ta 0 C 70 C 7 8 7 MHz 2 2V 5 5V Ta 40 C 85 C 10 8 10 MHz 5V Ta 25 C 20 12 20 MHz 5V Ta 25 C 20 16 20 MHz Frequency Accuracy trimmed 12MHz at VDD 3V Symbol Parameter Test Condi...

Page 21: ... MHz 5V 0 5V Ta 40 C 85 C 7 16 7 MHz 2 2V 5 5V Ta 0 C 70 C 7 16 7 MHz 2 2V 5 5V Ta 40 C 85 C 10 16 10 MHz 5V Ta 25 C 20 8 20 MHz 5V Ta 25 C 20 12 20 MHz A D Converter Electrical Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VDD Operating Voltage 2 2 5 5 V VADI Input Voltage 0 VR EF V VREF Reference Voltage 2 VDD V DNL Differential non linearity 2 2V 2 7V ...

Page 22: ... VBG Bandgap Reference Voltage 3 1 04 3 V IOP Operating Current 5V LVD LVR Enable VBGEN 0 20 25 μA 5V LVD LVR Enable VBGEN 1 180 200 μA tBGS VBG Turn on Stable Time No load 150 μs tLVDS LVDO stable time For LVR enable VBGEN 0 LVD off on 15 μs For LVR disable VBGEN 0 LVD off on 150 μs tLVR Minimum Low Voltage Width to Reset 120 240 480 μs tLVD Minimum Low Voltage Width to Interrupt 60 120 240 μs Co...

Page 23: ...50 75 μA ISEL 1 0 11 50 100 150 μA VLCD_H 2 3 VDD voltage for LCD SCOM SSEG output 2 2V 5 5V No load 0 645 0 67 0 698 VDD VLCD_L 1 3 VDD voltage for LCD SCOM SSEG output 2 2V 5 5V No load 0 305 0 33 0 355 VDD Power on Reset Characteristics Ta 25 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VPOR VDD Start Voltage to Ensure Power on Reset 100 mV RRVDD VDD Raising Rate to Ensure...

Page 24: ...ing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I O and A D control system with maximum reliability and flexibility This makes these devices suitable for low cost high volume production for controller applications Clocking and Pipelining The main system clock derived from either a HXT LXT H...

Page 25: ...ns requiring jumps to non consecutive addresses such as a jump instruction a subroutine call interrupt or reset etc the microcontroller manages program control by loading the required address into the Program Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy...

Page 26: ...wever when the stack is full a CALL subroutine instruction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is overflow the first Program Counter save in the stack will be lost Stack Pointer Stack Level Stack Level 1 Stack Level 3 Stack Level Pro ram Memory Pro ram Co nter Bott...

Page 27: ...16 HT66F0185 4K 16 Structure The Program Memory has a capacity of 2K 16 to 4K 16 bits The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries Table data which can be setup in any location within the Program Memory is addressed by a separate table pointer registers 000H Initialisation Vector 004H FFFH 16 bits Interr pt Vectors 0 4H Look ...

Page 28: ...ice This example uses raw table data located in the last page which is stored there using the ORG statement The value at this ORG statement is 0F00H which refers to the start address of the last page within the 4K Program Memory of the device The table pointer low byte register is setup here to have an initial value of 06H This will ensure that the first data read from the data table will be at th...

Page 29: ...nal convenience Holtek has provided a means of programming the microcontroller in circuit using a 4 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming or upgrading the program at a later stage This enables product manufacturers to easily keep their manufactured product...

Page 30: ... the On Chip Debug function Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT IDE development tools The OCDSDA pin is the OCDS Data Address input output pin while the OCDSCK pin is the OCDS clock input pin When users use the EV chip device for debugging the corresponding pin functions shared with the OCDSDA and OCDSC...

Page 31: ...er program control The overall Data Memory is subdivided into two banks The Special Purpose Data Memory registers are accessible in all banks with the exception of the EEC register at address 40H which is only accessible in Bank 1 Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value The start address of the Data Memory for the device is the...

Page 32: ... TM0DH TM0 L TM0 H TM0RPL TM0RPH Un sed read as 00H 36H 00H I R0 01H MP0 0 H I R1 03H MP1 04H 05H CC 06H PCL 0 H TBLP 0 H TBLH 09H TBHP 0 H ST TUS 0BH 0CH 0DH 0EH 0FH 10H INTC0 11H 1 H 19H P PU 1 H P WU 1BH 1 H 1DH 1CH 1FH P P C 13H 14H 15H 16H 1 H EE 0H 1H H H 3H 4H 5H 6H H 40H 41H 4 H 43H 44H 45H 46H 4 H 4 H 49H 4 H 4BH 4CH 4DH 4EH 4FH 50H 51H 53H 54H 1EH EEC Bank 0 1 55H 56H PBC PBPU PB FH BP L...

Page 33: ...to the registers indirectly will result in no operation Memory Pointers MP0 MP1 The Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers is carried...

Page 34: ...ting in higher programming and timing overheads Data transfer operations usually involve the temporary storage function of the Accumulator for example when transferring data between one user defined register and another it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted Program Counter Low Register PCL To provide addition...

Page 35: ...e latest operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation otherwise C is cleared C is also affected by a rotate through carry instruction AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction otherwise AC...

Page 36: ... overflow 1 An operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero flag 0 The result of an arithmetic or logical operation is not zero 1 The result of an arithmetic or logical operation is zero Bit 1 AC Auxiliary flag 0 No auxiliary carry 1 An operation results in a carry out of the low nibbles in addition or no borrow fro...

Page 37: ...to the EEPROM are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1 Device Capacity Address HT66F0175 64 8 00H 3FH HT66F0185 128 8 00H 7FH EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control register EEC...

Page 38: ...d 1 Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN has not first been set high Bit 1 RDEN Data EEPROM read enable 0 Disable 1 Enable This is the Data EEPROM Re...

Page 39: ...ill have been written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR bit will be automatically cleared to zero by the microcontroller informing the user that the data has been written to the EEPROM The application program can therefore poll the WR...

Page 40: ...ote that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete Otherwise the EEPROM read or write operation will fail Programming Example Reading data from the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer MP1 MOV MP1 A MP1 points to EEC register MOV A 01H setup Bank Pointer BP MOV B...

Page 41: ... fast and slow system clock the device has the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Type Name Frequency Pins High Speed External Crystal HXT 400 kHz 20 MHz OSC1 OSC2 High Speed Internal RC HIRC 8 12 16 MHz Low Speed External Crystal LXT 32 768 kHz XT1 XT2 Low Speed Internal RC LIRC 32 kHz Oscillator Types System...

Page 42: ...oscillation without requiring external capacitors However for some crystal types and frequencies to ensure oscillation it may be necessary to add two small value capacitors C1 and C2 Using a ceramic resonator will usually require two small value capacitors C1 and C2 to be connected as shown for oscillation to occur The values of C1 and C2 should be selected in consultation with the crystal or reso...

Page 43: ...ponents may be required to provide frequency compensation due to different crystal manufacturing tolerances During power up there is a time delay associated with the LXT oscillator waiting for it to start up When the microcontroller enters the SLEEP or IDLE Mode the system clock is switched off to stop microcontroller activity and to conserve power However in many microcontroller applications it m...

Page 44: ... power consumption must be kept to a minimum it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power on It should be noted that no matter what condition the LXTLP bit is set to the LXT oscillator will always function normally and the only difference is that it will take more time to start up if in the Low power mode Internal 32kHz Oscillator LIR...

Page 45: ...t and CKS2 CKS0 bits in the SMOD register The high speed system clock can be sourced from either an HXT or HIRC oscillator selected via a configuration option The low speed system clock source can be sourced from internal clock fSUB If fSUB is selected then it can be sourced by either the LXT or LIRC oscillator selected via a configuration option The other choice which is a divided version of the ...

Page 46: ...egister Although a high speed oscillator is used running the microcontroller at a divided clock ratio reduces the operating current SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source The clock source used will be from one of the low speed oscillators either the LXT or the LIRC Running the microcontroller in this mode allows it to...

Page 47: ...SUB 010 fH 64 011 fH 32 100 fH 16 101 fH 8 110 fH 4 111 fH 2 These three bits are used to select which clock is used as the system clock source In addition to the system clock source which can be either the LXT or LIRC a divided version of the high speed system oscillator can also be chosen as the system clock source Bit 4 FSTEN Fast Wake up Control only for HXT 0 Disable 1 Enable This is the Fast...

Page 48: ...al functions operational if the FSYSON bit is high If the FSYSON bit is low the CPU and the system clock will all stop in IDLE0 mode If the bit is low the devices will enter the SLEEP mode when a HALT instruction is executed Bit 0 HLCLK System clock selection 0 fH 2 fH 64 or fSUB 1 fH This bit is used to select if the fH clock or the fH 2 fH 64 or fSUB clock is used as the system clock When the bi...

Page 49: ...on is enabled then it will take one to two tSUB clock cycles of the LIRC or LXT oscillator for the system to wake up The system will then initially run under the fSUB clock source until 512 HXT clock cycles have elapsed at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator If the HIRC oscillator or LIRC oscillator is used as the system os...

Page 50: ...it in the SMOD register and the FSYSON bit in the CTRL register When the HLCLK bit switches to a low level which implies that clock source is switched from the high speed clock fH to the clock source fH 2 fH 64 or fSUB If the clock is from the fSUB the high speed clock source will stop running to conserve power When this happens it must be noted that the fH 16 and fH 64 internal clock sources will...

Page 51: ...ecide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the configuration option and therefore requires this oscillator to be stable before full mode switching occurs This is monitored using the LTO bit in the SMOD register NORMAL Mode SLOW Mode CKS CKS0 00xB H...

Page 52: ...ruction is executed WDT is on IDLEN 1 FSYSON 0 HALT instruction is executed IDLEN 1 FSYSON 1 HALT instruction is executed Entering the SLEEP0 Mode There is only one way for the devices to enter the SLEEP0 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in the SMOD register equal to 0 and the WDT and LVD both off When this instruction is executed under...

Page 53: ... register equal to 0 When this instruction is executed under the conditions described above the following will occur The system clock will be stopped and the application program will stop at the HALT instruction but the fTBC and fSUB clocks will be on The Data Memory contents and registers will maintain their present condition The WDT will be cleared and resume counting if the WDT function is enab...

Page 54: ...a considerable time for the original system oscillator to restart stablise and allow normal operation to resume After the system enters the SLEEP or IDLE Mode it can be woken up from one of various sources listed as follows An external falling edge on Port A A system interrupt A WDT overflow When the devices execute the HALT instruction it will enter the Power down mode and the PDF flag will be se...

Page 55: ...system clock source is switched from fH to fSUB the clock source to the peripheral functions mentioned above will change accordingly The on off condition of fSUB and fS depends upon whether the WDT is enabled or disabled as the WDT clock source is selected from fSUB Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations due to c...

Page 56: ...10 fSUB 010 212 fSUB 011 214 fSUB 100 215 fSUB 101 216 fSUB 110 217 fSUB 111 218 fSUB These three bits determine the division ratio of the watchdog timer source clock which in turn determines the time out period CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON LVRF LRF WRF R W R W R W R W R W POR 0 x 0 0 x unknown Bit 7 FSYSON fSYS Control in IDLE Mode Described elsewhere Bit 6 3 Unimplemented read a...

Page 57: ...ts will have a value of 01010B WE4 WE0 Bits WDT Function 10101B Disable 01010B Enable Any other value Reset MCU Watchdog Timer Enable Disable Control Under normal program operation a Watchdog Timer time out will initialise a device reset and set the status bit TO However if the system is in the SLEEP or IDLE Mode when a Watchdog Timer time out occurs the TO bit in the status register will be set a...

Page 58: ... well as ensuring that the Program Memory begins execution from the first memory address a power on reset also ensures that certain other registers are preset to known conditions All the I O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs VDD Power on Reset SST Time o t tRSTD Note tRSTD is power on delay with typical time 50 ms P...

Page 59: ... the four defined register values above will also result in the generation of an MCU reset The reset operation will be activated after 2 3 fLIRC clock cycles However in this situation the register contents will be reset to the POR value CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON LVRF LRF WRF R W R W R W R W R W POR 0 x 0 0 x unknown Bit 7 FSYSON fSYS Control in IDLE Mode Described elsewhere Bit...

Page 60: ...er operations such as the SLEEP or IDLE Mode function or Watchdog Timer The reset flags are shown in the table TO PDF Reset Function 0 0 Power on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time out reset during NORMAL or SLOW Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation u stands for unchanged The following table indicates the way in which the vari...

Page 61: ...uu MFI0 0 0 0 0 0 0 0 0 0 0 0 0 uu uu MFI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu MFI2 0 0 0 0 0 0 0 0 0 0 0 0 uu uu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PAPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu PAWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TMPC 0 0 0 0 0 0 0 0 0 u uu TMPC 0 0 0 0 0 0 0 0 0 ...

Page 62: ... uuuu uuuu TM0DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM0AL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM0AH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM0RP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu u TM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu TM1DL 0 0 0 0 0 0 0 0 0 0 ...

Page 63: ... 0 1 uuuu IFS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uu uuuu IFS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuu uuuu PD 1 1 1 1 1 1 1 1 1 1 1 1 uuuu PDC 1 1 1 1 1 1 1 1 1 1 1 1 uuuu PDPU 0 0 0 0 0 0 0 0 0 0 0 0 uuuu USR 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 uuuu uuuu UCR1 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 x 0 uuuu uuuu UCR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuu BRG...

Page 64: ...emory table All of these I O ports can be used for input and output operations For input operation these ports are non latching which means the inputs must be ready at the T2 rising edge of instruction MOV A m where m denotes the port address For output operation all the data is latched and remains unchanged until the output latch is rewritten Register Name Bit 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAW...

Page 65: ...ata 1 PACn PBCn PCCn PDCn I O Pin type selection 0 Output 1 Input Pull high Resistors Many product applications require pull high resistors for their switch inputs usually requiring the use of an external resistor To eliminate the need for these external resistors all I O pins when configured as an input have the capability of being connected to an internal pull high resistor These pull high resis...

Page 66: ...ster SLEDC0 and SLEDC1 each I O port can support four levels of the source current driving capability Users should refer to the D C characteristics section to select the desired source current for different applications Register Name Bit 7 6 5 4 3 2 1 0 SLEDC0 PBPS3 PBPS2 PBPS1 PBPS0 PAPS3 PAPS2 PAPS1 PAPS0 SLEDC1 HT66F0175 PCPS3 PCPS2 PCPS1 PCPS0 SLEDC1 HT66F0185 PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCP...

Page 67: ...rent Level 2 11 source current Level 3 max SLEDC1 Register HT66F0185 Bit 7 6 5 4 3 2 1 0 Name PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCPS0 R W R W R W R W R W R W R W POR 0 1 0 1 0 1 Bit 7 6 Unimplemented read as 0 Bit 5 4 PDPS1 PDPS0 PD3 PD0 source current selection 00 source current Level 0 min 01 source current Level 1 10 source current Level 2 11 source current Level 3 max Bit 3 2 PCPS3 PCPS2 PC6 PC4 s...

Page 68: ... selection a wide range of different functions can be incorporated into even relatively small package sizes If the pin shared pin function have multiple outputs simultaneously its pin names at the right side of the sign can be used for higher priority Register Name Bit 7 6 5 4 3 2 1 0 IFS HT66F0175 SDOPS SDI_SDAPS SCK_SCLPS SCSBPS INT1PS INT0PS IFS HT66F0185 SDOPS1 SDOPS0 SDI_SDAPS SCK_SCLPS SCSBP...

Page 69: ...LPS SCK SCL pin remapping selection 0 SCK CL on PC5 1 SCK CL on PB6 Bit 2 SCSBPS SCS pin remapping selection 0 SCS on PC6 1 SCS on PB5 Bit 1 TXPS TX pin remapping selection 0 TX on PD2 1 TX on PB3 Bit 0 RXPS RX pin remapping selection 0 RX on PD1 1 RX on PB4 I O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I O pin types As the exact logical constructi...

Page 70: ...bit control instructions a read modify write operation takes place The microcontroller must first read in the data on the entire port modify it to the required new bit values and then rewrite this data back to the output ports The power on reset condition of the A D converter control registers ensures that any A D input pins which are always shared with other I O functions will be setup as analog ...

Page 71: ...eriodic TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections The main features and differences between the three types of TMs are summarised in the accompanying table TM Function CTM STM PTM Timer Counter Input Capture Compare Match Output PWM Channels 1 1 1 Single Pulse Output 1 1 PWM Alignment Edge Edge Edge PWM Ad...

Page 72: ...g the TnCK2 TnCK0 bits The TM input pin can be chosen to have either a rising or falling active edge The TCKn pin is also used as the external trigger input pin in single pulse output mode for the STM and PTM respectively The TMs each have one output pin with the label TPn When the TM is in the Compare Match Output Mode these pins can be controlled by the TM to switch to a high or low level or to ...

Page 73: ...n shared function selection are described in the pin shared function section Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMPC HT66F0175 CLOP T1CP T0CP TMPC HT66F0185 CLOP T2CP T1CP T0CP TM Pin Control Register List TM0 PTM P 0 TP0 T0CP P 0 O tp t F nction 0 1 O tp t Capt re Inp t T0C PTS PB TCK0 TCK Inp t 0 1 P 0 0 1 1 0 TM0 Function Pin Control Block Diagram HT66F0175 only TM0 STM P 0 T...

Page 74: ...put TMPC Register HT66F0175 Bit 7 6 5 4 3 2 1 0 Name CLOP T1CP T0CP R W R W R W R W POR 0 0 0 Bit 7 CLOP CLO pin control 0 Disable 1 Enable Bit 6 2 Unimplemented read as 0 Bit 1 T1CP TP1 pin control 0 Disable 1 Enable Bit 0 T0CP TP0 pin control 0 Disable 1 Enable TMPC Register HT66F0185 Bit 7 6 5 4 3 2 1 0 Name CLOP T2CP T1CP T0CP R W R W R W R W R W POR 0 0 0 0 Bit 7 CLOP CLO pin control 0 Disabl...

Page 75: ... low byte registers named TMnAL and TMnRPL using the following access procedures Accessing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values Data B s bit B ffer TMnDH TMnDL TMn H TMn L TMn Co nter Re ister Read only TMn CCR Re ister Read Write TMnRPH TMnRPL PTM CCRP Re ister Read Write The following steps show the read and write proce...

Page 76: ...F0185 only Compact TM Operation The Compact TM core is a 16 bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP is eight bit wide whose value is compared with the highest eight bits...

Page 77: ...D6 D5 D4 D3 D2 D1 D0 TMnAH D15 D14 D13 D12 D11 D10 D9 D8 TMnRP TnRP7 TnRP6 TnRP5 TnRP4 TnRP3 TnRP2 TnRP1 TnRP0 16 bit Compact TM Registers List n 2 for for HT66F0185 only TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 TMn Counter Low Byte Register bit 7 bit 0 TMn 16 bit Counter bit 7 bit 0 TMnDH Register Bit 7 6 5 4 3 2 1 0 Name D15 ...

Page 78: ...for the TMn The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fTBC are other internal clocks the details of which can be found in the oscillator section Bit 3 TnON TMn Counter On Off control 0 Off 1 On This bit controls the overall on off function of the TMn Setting the bit high enables the counter to run w...

Page 79: ...running In the Compare Match Output Mode the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A The TMn output pin can be setup to switch high switch low or to toggle its present state when a compare match occurs from the Comparator A When the bits are both zero then no change will take place on the output The initial value of the ...

Page 80: ...rs the counter Remember that the Compact TM contains two comparators Comparator A and Comparator P either of which can be selected to clear the internal counter With the TnCCLR bit set high the counter will be cleared when a compare match occurs from the Comparator A When the bit is low the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow A count...

Page 81: ...ever here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when TnCCLR is high no TMnPF interrupt request flag will be generated If the CCRA bits are all zero the counter will overflow when its reaches its maximum 1 bit FFFF Hex value however here the TnAF interrupt request flag will not be generated As the ...

Page 82: ... 0 Output Toggle with TnAF flag Note TnIO 1 0 10 Active High Output select Here TnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high Compare Match Output Mode TnCCLR 0 Note 1 With TnCCLR 0 a Comparator P match will clear the counter 2 ...

Page 83: ...ut select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high TnPF not generated No TnAF flag generated on CCRA overflow Output does not change CCRA Int flag TnAF CCRP Int flag TnPF Compare Match Output Mode TnCCLR 1 Note 1 With TnCCLR 1 a Comparator A match will cle...

Page 84: ...ed to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA an...

Page 85: ...1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when TnPOL 1 PWM Period set by CCRP TMn O P Pin TnOC 0 CCRA Int flag TnAF CCRP Int flag TnPF PWM Output Mode TnDPX 0 Note 1 Here TnDPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues even when TnIO 1 0 00 or 01 4 The TnCCLR bit has ...

Page 86: ...et when TnON returns high TnDPX 1 TnM 1 0 10 PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when TnPOL 1 PWM Period set by CCRA TMn O P Pin TnOC 0 PWM Output Mode TnDPX 1 Note 1 Here TnDPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even when TnIO 1 0 00 or 01 4 The TnCCLR bit has ...

Page 87: ...Standard TM Operation The size of Standard TM is 16 bit wide and its core is a 16 bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 8 bit wide whose value is compare...

Page 88: ...0 TMnAH D15 D14 D13 D12 D11 D10 D9 D8 TMnRP TnRP7 TnRP6 TnRP5 TnRP4 TnRP3 TnRP2 TnRP1 TnRP0 16 bit Standard TM Registers List n 0 for HT66F0185 only TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 TMn Counter Low Byte Register bit 7 bit 0 TMn 16 bit Counter bit 7 bit 0 TMnDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9...

Page 89: ...for the TMn The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fTBC are other internal clocks the details of which can be found in the oscillator section Bit 3 TnON TMn Counter On Off control 0 Off 1 On This bit controls the overall on off function of the TMn Setting the bit high enables the counter to run w...

Page 90: ...anges state when a certain condition is reached The function that these bits select depends upon in which mode the TMn is running In the Compare Match Output Mode the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A The TM output pin can be setup to switch high switch low or to toggle its present state when a compare match occurs...

Page 91: ...output pin will be inverted and not inverted when the bit is zero It has no effect if the TMn is in the Timer Counter Mode Bit 1 TnDPX TMn PWM duty period control 0 CCRP period CCRA duty 1 CCRP duty CCRA period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform Bit 0 TnCCLR TMn Counter Clear condition selection 0 Comparator P match 1 C...

Page 92: ...ompare match from Comparator A and a compare match from Comparator P When the TnCCLR bit is low there are two ways in which the counter can be cleared One is when a compare match from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively will both be generated If ...

Page 93: ...utput Toggle with TnAF flag Note TnIO 1 0 10 Active High Output select Here TnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high Compare Match Output Mode TnCCLR 0 Note 1 With TnCCLR 0 a Comparator P match will clear the counter 2 The ...

Page 94: ...select Here TnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high TnPF not generated No TnAF flag generated on CCRA overflow Output does not change Compare Match Output Mode TnCCLR 1 Note 1 With TnCCLR 1 a Comparator A match will clear ...

Page 95: ...e CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register The PWM waveform frequency and duty cycle can therefore be control...

Page 96: ...n TnON returns high TnDPX 0 TnM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when TnPOL 1 PWM Period set by CCRP TMn O P Pin TnOC 0 PWM Output Mode TnDPX 0 Note 1 Here TnDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when TnIO 1 0 00 or 01 4 The TnCCLR bi...

Page 97: ... when TnON returns high TnDPX 1 TnM 1 0 10 PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when TnPOL 1 PWM Period set by CCRA TMn O P Pin TnOC 0 PWM Output Mode TnDPX 1 Note 1 Here TnDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when TnIO 1 0 00 or 01 4 The TnCCLR bit ha...

Page 98: ...ading edge will be generated The TnON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the TnON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the S...

Page 99: ...ut Inverts when TnPOL 1 No CCRP Interrupts generated TMn O P Pin TnOC 0 TCKn pin Software Trigger Cleared by CCRA match TCKn pin Trigger Auto set by TCKn pin Software Trigger Software Clear Software Trigger Software Trigger Single Pulse Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the TCKn pin or by setting the TnON bit high 4 A TCKn pin active edge will automati...

Page 100: ...in the present value in the counter will be latched into the CCRA registers and a TMn interrupt generated Irrespective of what events occur on the TPn pin the counter will continue to free run until the TnON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compar...

Page 101: ...ue XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 TnM 1 0 01 and active edge set by the TnIO 1 0 bits 2 A TMn Capture input pin active edge transfers the counter value to CCRA 3 TnCCLR bit not used 4 No output function TnOC and TnPOL bits are not used 5 CCRP determines the counter value and the counter has a...

Page 102: ...TM Block Diagram n 0 or 1 Periodic TM Operation The size of Periodic TM is 10 bit wide and its core is a 10 bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP and CCRA comparators ...

Page 103: ...it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMnC0 TnPAU TnCK2 TnCK1 TnCK0 TnON TMnC1 TnM1 TnM0 TnIO1 TnIO0 TnOC TnPOL TnCAPTS TnCCLR TMnDL D7 D6 D5 D4 D3 D2 D1 D0 TMnDH D9 D8 TMnAL D7 D6 D5 D4 D3 D2 D1 D0 TMnAH D9 D8 TMnRPL TnRP7 TnRP6 TnRP5 TnRP4 TnRP3 TnRP2 TnRP1 TnRP0 TMnRPH TnRP9 TnRP8 Periodic TM Registers List n 0 or 1 TMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R ...

Page 104: ...0 Bit 7 2 Unimplemented read as 0 Bit 1 0 TMn CCRA High Byte Register bit 1 bit 0 TMn 10 bit CCRA bit 9 bit 8 TMnRPL Register Bit 7 6 5 4 3 2 1 0 Name TnRP7 TnRP6 TnRP5 TnRP4 TnRP3 TnRP2 TnRP1 TnRP0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 TnRP7 TnRP0 TMn CCRP Low Byte Register bit 7 bit 0 TMn 10 bit CCRP bit 7 bit 0 TMnRPH Register Bit 7 6 5 4 3 2 1 0 Name TnRP9 TnRP8 R W R...

Page 105: ... for the TMn The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fTBC are other internal clocks the details of which can be found in the oscillator section Bit 3 TnON TMn Counter On Off control 0 Off 1 On This bit controls the overall on off function of the TMn Setting the bit high enables the counter to run ...

Page 106: ...tput pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the TMn is running In the Compare Match Output Mode the TnIO1 and TnIO0 bits determine how the TMn output pin changes state when a compare match occurs from the Comparator A The TMn output pin can be setup to switch high switch low or to toggle its present state when a compare ...

Page 107: ...rity of the TPn output pin When the bit is set high the TMn output pin will be inverted and not inverted when the bit is zero It has no effect if the TMn is in the Timer Counter Mode Bit 1 TnCAPTS TMn Capture Trigger Source selection 0 From TPn pin 1 From TCKn pin Bit 0 TnCCLR TMn Counter Clear condition selection 0 Comparator P match 1 Comparator A match This bit is used to select the method whic...

Page 108: ...the counter will be cleared when a compare match occurs from Comparator A However here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when TnCCLR is high no TnPF interrupt request flag will be generated In the Compare Match Output Mode the CCRA can not be set to 0 As the name of the mode suggests after a c...

Page 109: ...with TnAF flag Note TnIO 1 0 10 Active High Output select Here TnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high Compare Match Output Mode TnCCLR 0 Note 1 With TnCCLR 0 a Comparator P match will clear the counter 2 The TMn output pi...

Page 110: ...TnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by TnON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when TnPOL is high TnPF not generated No TnAF flag generated on CCRA overflow Output does not change Compare Match Output Mode TnCCLR 1 Note 1 With TnCCLR 1 a Comparator A match will clear the counter ...

Page 111: ... DC RMS values As both the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM mode the TnCCLR bit has no effect as the PWM period Both of the CCRP and CCRA registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is use...

Page 112: ...when TnON returns high TnM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts When TnPOL 1 PWM Period set by CCRP TMn O P Pin TnOC 0 PWM Mode Note 1 The counter is cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when TnIO 1 0 00 or 01 4 The TnCCLR bit has no influence on PWM ...

Page 113: ...pulse leading edge will be generated The TnON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the TnON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the TnON bit and thus genera...

Page 114: ...hen TnPOL 1 No CCRP Interrupts generated TMn O P Pin TnOC 0 TCKn pin Software Trigger Cleared by CCRA match TCKn pin Trigger Auto set by TCKn pin Software Trigger Software Clear Software Trigger Software Trigger Single Pulse Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the TCKn pin or by setting the TnON bit high 4 A TCKn pin active edge will automatically set th...

Page 115: ...rated Irrespective of what events occur on the TPn or TCKn pin the counter will continue to free run until the TnON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a TMn interrupt will also be generated Counting the number ...

Page 116: ... XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note 1 TnM 1 0 01 and active edge set by the TnIO 1 0 bits 2 A TMn Capture input pin active edge transfers the counter value to CCRA 3 TnCCLR bit not used 4 No output function TnOC and TnPOL bits are not used 5 CCRP determines the counter value and the counter has a maximum...

Page 117: ... signal to be converted is determined by the SAINS2 SAINS0 bits together with the SACS2 SACS0 bits Note that when the external and internal analog signals are simultaneously selected to be converted the internal analog signal will have the priority In the meantime the external analog signal will temporarily be switched off until the internal analog signal is deselected More detailed information ab...

Page 118: ...CERL ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 A D Converter Registers List A D Converter Data Registers SADOL SADOH As these devices contain an internal 12 bit A D converter it requires two data registers to store the converted value These are a high byte register known as SADOH and a low byte register known as SADOL After the conversion process takes place these registers can be directly read by t...

Page 119: ...be converted If the SAINS2 SAINS0 bits are set to any other values except 000 and 100 one of the internal analog signals can be selected to be converted The internal analog signals can be derived from the A D converter supply power VDD or internal reference voltage VR with a specific ratio of 1 1 2 or 1 4 If the internal analog signal is selected to be converted the external channel signal input w...

Page 120: ...is initiated The ADBZ flag will be cleared to 0 after the A D conversion is complete Bit 5 ADCEN A D Converter function enable control 0 Disable 1 Enable This bit controls the A D internal function This bit should be set to one to enable the A D converter If the bit is set low then the A D converter will be switched off reducing the device power consumption When the A D converter function is disab...

Page 121: ...e VDD 4 101 Internal signal Internal reference voltage VR 110 Internal signal Internal reference voltage VR 2 111 Internal signal Internal reference voltage VR 4 When the internal analog signal is selected to be converted the external channel input signal will automatically be switched off regardless of the SACS2 SACS0 bit field value The internal reference voltage can be derived from various sour...

Page 122: ...e bit is set high the Bandgap reference voltage can be used by the A D converter If the Bandgap reference voltage is not used by the A D converter and the LVD or LVR function is disabled then the bandgap reference circuit will be automatically switched off to conserve power When the Bandgap reference voltage is switched on for use by the A D converter a time tBGS should be allowed for the Bandgap ...

Page 123: ...e PA7 is A D input or not 0 Not A D input 1 A D input AN6 Bit 5 ACE5 Define PA6 is A D input or not 0 Not A D input 1 A D input AN5 Bit 4 ACE4 Define PA5 is A D input or not 0 Not A D input 1 A D input AN4 Bit 3 ACE3 Define PA4 is A D input or not 0 Not A D input 1 A D input AN3 Bit 2 ACE2 Define PB2 is A D input or not 0 Not A D input 1 A D input AN2 Bit 1 ACE1 Define PB1 is A D input or not 0 No...

Page 124: ...n external reference source supplied on pin VREFI or an internal reference source derived from the Bandgap circuit Then the selected reference voltage source can be amplified through a programmable gain amplifier except the voltage sourced from VDD The PGA gain can be equal to 1 2 3 or 4 The desired selection is made using the SAVRS3 SAVRS0 bits in the SADC2 register and relevant pin shared functi...

Page 125: ...ns 167ns 333ns 667ns 1 33μs 2 67μs 5 33μs 10 67μs 16 MHz 62 5ns 125ns 250ns 500ns 1μs 2μs 4μs 8μs 20 MHz 50ns 100ns 200ns 400ns 800ns 1 6μs 3 2μs 6 4μs A D Clock Period Examples Controlling the power on off function of the A D converter circuitry is implemented using the ADCEN bit in the SADC0 register This bit must be set high to power on the A D converter When the ADCEN bit is set high to power ...

Page 126: ... to the internal A D converter by correctly configuring the SAINS2 SAINS0 bits Select the external channel input to be converted go to Step 4 Select the internal analog signal to be converted go to Step 5 Step 4 If the A D input signal comes from the external channel input selecting by configuring the SAINS bit field the corresponding pins should first be configured as A D input function by config...

Page 127: ...er consumption by setting bit ADCEN low in the SADC0 register When this happens the internal A D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines If the A D converter input lines are used as normal I Os then care must be taken as if the input voltage is not at a valid logic level then this may lead to some increase in power consumption A...

Page 128: ...ADC interrupt mov a 03H mov SADC1 a select fSYS 8 as A D clock and switch off VBG voltage set ADCEN mov a 03H setup ACERL to configure pin AN0 mov ACERL a mov a 00H mov SADC0 a enable and connect AN0 channel to A D converter start_conversion clr START high pulse on start bit to initiate conversion set START reset A D clr START start A D polling_EOC sz ADBZ poll the SADC0 register ADBZ bit to detec...

Page 129: ...ion set START reset A D clr START start A D clr ADF clear ADC interrupt request flag set ADE enable ADC interrupt set EMI enable global interrupt ADC_ISR ADC interrupt service routine mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a SADOL read low byte conversion result value mov SADOL_buffer a save result to user defined regi...

Page 130: ...ugh the SPI interface specification can control multiple slave devices from a single master these devices provided only one SCS pin If the master needs to control multiple slave devices from a single master the master can use I O pin to select the slave devices SPI Interface Operation The SPI interface is a full duplex synchronous serial data link It is a four line interface with pin names SDI SDO...

Page 131: ...C2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SIMD D7 D6 D5 D4 D3 D2 D1 D0 SPI Registers List SIMD Register The SIMD register is used to store the data being transmitted and received The same register is used by both the SPI and I2 C functions Before the devices write data to the SPI bus the actual data to be transmitted must be placed in the SIMD register After the data is received from the SPI bus the ...

Page 132: ...stem clock debounce Bit 1 SIMEN SIM Enable Control 0 Disable 1 Enable The bit is the overall on off control for the SIM interface When the SIMEN bit is cleared to zero to disable the SIM interface the SDI SDO SCK and SCS or SDA and SCL lines will lose their SPI or I2 C function and the SIM operating current will be reduced to a minimum value When the bit is high the SIM interface is enabled If the...

Page 133: ...the clock line if the bit is high then the SCK line will be low when the clock is inactive When the CKPOLB bit is low then the SCK line will be high when the clock is inactive The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit Bit 3 MLS SPI data shift order 0 LSB first 1 MSB first This is the data shift select bit and is used to select how the data is tra...

Page 134: ...SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register The master should output a SCS signal to enable the slave devices before a clock signal is provided The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit The accompanying timing ...

Page 135: ...Rev 1 50 135 August 28 2017 HT66F0175 HT66F0185 A D Flash MCU with EEPROM SPI Slave Mode Timing CKEG 1 SPI Transfer Control Flow Chart ...

Page 136: ...ace a serial data line SDA and serial clock line SCL As many devices may be connected together on the same bus their outputs are both open drain types For this reason it is necessary that external pull high resistors are connected to these outputs Note that no chip select line exists as each device on the I2 C bus is identified by a unique address which will be transmitted and received on the I2 C...

Page 137: ...100kHz I2 C Fast Mode 400kHz No Devounce fSYS 2 MHz fSYS 5 MHz 2 system clock debounce fSYS 4 MHz fSYS 10 MHz 4 system clock debounce fSYS 8 MHz fSYS 20 MHz I2 C Minimum fSYS Frequency I2 C Registers There are three control registers associated with the I2 C bus SIMC0 SIMC1 and SIMTOC one slave address register SIMA and one data register SIMD The SIMD register which is shown in the above SPI secti...

Page 138: ... define the device slave address Bit 0 is not defined When a master device which is connected to the I2 C bus sends out an address which matches the slave address in the SIMA register the slave device will be selected Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface Bit 7 6 5 4 3 2 1 0 Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0 R W R W R W...

Page 139: ...A and SCL lines will lose their SPI or I2 C function and the SIM operating current will be reduced to a minimum value When the bit is high the SIM interface is enabled If the SIM is configured to operate as an SPI interface via the SIM2 SIM0 bits the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first ...

Page 140: ...lave send acknowledge flag 1 Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag After the slave device receipt of 8 bits of data this bit will be transmitted to the bus on the 9th clock from the slave device The slave device must always set TXAK bit to 0 before further data is received Bit 2 SRW I2 C slave read write flag 0 Slave device should be in receive mode 1 S...

Page 141: ...on the bus The first seven bits of the data will be the slave address with the first bit being the MSB If the address of the slave device matches that of the transmitted address the HAAS bit in the SIMC1 register will be set and an I2 C interrupt will be generated After entering the interrupt service routine the slave device must first check the condition of the HAAS and SIMTOF bits to determine w...

Page 142: ...a byte transfer or the I2 C bus time out occurrence When a slave address is matched the devices must be placed in either the transmit mode and then write data to the SIMD register or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line I2 C Bus Read Write Signal The SRW bit in the SIMC1 register defines whether the master device wishes to read dat...

Page 143: ...ta will be stored in the SIMD register If setup as a transmitter the slave device must first write the data to be transmitted into the SIMD register If setup as a receiver the slave device must read the transmitted data from the SIMD register When the slave receiver receives the data byte it must generate an acknowledge bit known as TXAK on the 9th clock The slave device which is setup as a transm...

Page 144: ...e I2 C bus is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts to count on an I2 C bus START address match condition and is cleared by an SCL falling edge Before the next SCL falling edge arrives if the time elapsed is greater than the time out period specified by the SIMTOC register then a time out condition w...

Page 145: ...ters will be reset into the following condition Register After I2 C Time out SIMD SIMA SIMC0 No change SIMC1 Reset to POR condition I2 C Register after Time out The SIMTOF flag can be cleared by the application program There are 64 time out period selections which can be selected using the SIMTOS bits in the SIMTOC register The time out duration is calculated by the formula 1 64 32 fSUB This gives...

Page 146: ...ive feedback to the comparator Ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level However unavoidable input offsets introduce some uncertainties here The hysteresis function if enabled also increases the switching offset value Comparator Interrupt The comparator possesses its own interrupt function When the comparator outp...

Page 147: ...arator polarity bit If the bit is zero then the COUT bit will reflect the non inverted output condition of the comparator If the bit is high the comparator COUT bit will be inverted Bit 4 COUT Comparator Output bit CPOL 0 0 C C 1 C C CPOL 1 0 C C 1 C C This bit stores the comparator output bit The polarity of the bit is determined by the voltages on the comparator inputs and by the condition of th...

Page 148: ...ling the overall on off function also controls the R type bias current on the SCOM and SSEG pins This enables the LCD COM and SEG driver to generate the necessary VSS 1 3 VDD 2 3 VDD and VDD voltage levels for LCD 1 3 bias operation The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver This bit is used in conjunction with the COMnEN and SEGnEN bits to select which I...

Page 149: ...e FRAME bit and the corresponding pin shared I O data bit for the respective SEG pin to determine whether the SEGm output has a value of VDD VSS or VBIAS The accompanying waveform diagram shows a typical 1 3 bias LCD waveform generated using the application program together with the LCD voltage select circuit Note that the depiction of a 1 in the diagram illustrates an illuminated LCD pixel The CO...

Page 150: ...CDEN COM3EN COM2EN COM1EN COM0EN SLCDC1 COM5EN COM4EN COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS2 COMSEGS1 COMSEGS0 SLCDC2 SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN SEG8EN SEG7EN SEG6EN SLCDC3 SEG21EN SEG20EN SEG19EN SEG18EN SEG17EN SEG16EN SEG15EN SEG14EN SLCDC4 SEG23EN SEG22EN LCD Driver Control Registers List HT66F0185 SLCDC0 Register Bit 7 6 5 4 3 2 1 0 Name FRAME ISEL1 ISEL0 LCDEN COM3EN COM2EN COM1EN C...

Page 151: ... W POR 0 0 0 0 0 0 0 0 Bit 7 COM5EN SCOM5 SSEG5 or other pin function select 0 Other pin shared functions 1 SCOM5 SSEG5 function Bit 6 COM4EN SCOM4 SSEG4 or other pin function select 0 Other pin shared functions 1 SCOM4 SSEG4 function Bit 5 COMSEGS5 SCOM5 or SSEG5 pin function select 0 SCOM5 1 SSEG5 Bit 4 COMSEGS4 SCOM4 or SSEG4 pin function select 0 SCOM4 1 SSEG4 Bit 3 COMSEGS3 SCOM3 or SSEG3 pin...

Page 152: ...0 Other pin shared functions 1 SSEG12 function Bit 5 SEG11EN SSEG11 pin function select 0 Other pin shared functions 1 SSEG11 function Bit 4 SEG10EN SSEG10 pin function select 0 Other pin shared functions 1 SSEG10 function Bit 3 SEG9EN SSEG9 pin function select 0 Other pin shared functions 1 SSEG9 function Bit 2 SEG8EN SSEG8 pin function select 0 Other pin shared functions 1 SSEG8 function Bit 1 S...

Page 153: ...ct 0 Other pin shared functions 1 SSEG19 function Bit 4 SEG18EN SSEG18 pin function select 0 Other pin shared functions 1 SSEG18 function Bit 3 SEG17EN SSEG17 pin function select 0 Other pin shared functions 1 SSEG17 function Bit 2 SEG16EN SSEG16 pin function select 0 Other pin shared functions 1 SSEG16 function Bit 1 SEG15EN SSEG15 pin function select 0 Other pin shared functions 1 SSEG15 functio...

Page 154: ...N SSEG18 pin function select 0 Other pin shared functions 1 SSEG18 function Bit 3 SEG17EN SSEG17 pin function select 0 Other pin shared functions 1 SSEG17 function Bit 2 SEG16EN SSEG16 pin function select 0 Other pin shared functions 1 SSEG16 function Bit 1 SEG15EN SSEG15 pin function select 0 Other pin shared functions 1 SSEG15 function Bit 0 SEG14EN SSEG14 pin function select 0 Other pin shared ...

Page 155: ...en a reception occurs or when a transmission terminates The integrated UART function contains the following features Full duplex asynchronous communication 8 or 9 bits character length Even odd or no parity options One or two stop bits Baud rate generator with 8 bit prescaler Parity framing noise and overrun error detection Support for interrupt on address detect last character bit 1 Separately en...

Page 156: ...am Data to be received by the UART is accepted on the external RX pin from where it is shifted in LSB first to the Receiver Shift Register at a rate controlled by the Baud Rate Generator When the shift register is full the data will then be transferred from the shift register to the internal RXR register where it is buffered and can be manipulated by the application program Only the TXR register i...

Page 157: ...rity of the received word is incorrect This error flag is applicable only if Parity mode odd or even is selected The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register Bit 6 NF Noise flag 0 No noise is detected 1 Noise is detected The NF flag is the noise flag When this read only flag is 0 it indicates no ...

Page 158: ...nterrupt is generated if RIE 1 in the UCR2 register If one or more errors are detected in the received word the appropriate receive related flags NF FERR and or PERR are set within the same clock cycle The RXIF flag is cleared when the USR register is read with RXIF set followed by a read from the RXR register and if the RXR register has no data available Bit 1 TIDLE Transmission status 0 Data tra...

Page 159: ... and BRG registers will remain unaffected If the UART is active and the UARTEN bit is cleared all pending transmissions and receptions will be terminated and the module will be reset as defined above When the UART is re enabled it will restart in the same configuration Bit 6 BNO Number of data transfer bits selection 0 8 bit data transfer 1 9 bit data transfer This bit is used to select the data l...

Page 160: ...o serves to control the baud rate speed receiver wake up function enable and the address detect function enable Further explanation on each of the bits is given below Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN UART Transmitter enable control 0 UART Transmitter is disabled 1 UART Transmitter is enabled The TXEN...

Page 161: ...r wake up function If this bit is equal to 1 and the device is in IDLE0 or SLEEP mode a falling edge on the RX pin will wake up the device If this bit is equal to 0 and the device is in the power down mode any edge transitions on the RX pin will not wake up the device Bit 2 RIE Receiver interrupt enable control 0 Receiver related interrupt is disabled 1 Receiver related interrupt is enabled The bi...

Page 162: ...equired baud rate can be setup Note that because the actual baud rate is determined using a discrete value N placed in the BRG register there will be an error associated between the actual and requested value The following example shows how the BRG register value N and the error value can be calculated BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R W R W R W R W R ...

Page 163: ...ed functional pins When the UART function is disabled the buffer will be reset to an empty condition at the same time discarding any remaining residual data Disabling the UART will also reset the enable control the error and status flags with bits TXEN RXEN TXBRK RXIF OERR FERR PERR and NF being cleared while bits TIDLE TXIF and RIDLE will be set The remaining control bits in the UCR1 UCR2 and BRG...

Page 164: ...ed until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source However the transmission can also be initiated by first loading data into the TXR register after which the TXEN bit can be set When a transmission of data begins the TSR is normally empty in which case a transfer to the TXR register will result in an immediate transfer to the TSR If dur...

Page 165: ...e that a break condition length is at least 13 bits long If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters After the application program has cleared the TXBRK bit the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits The automatic logic high at the end of the...

Page 166: ... the values programmed into the BNO and STOPS bits If the break is much longer than 13 bit times the reception will be considered as complete after the number of bit times specified by BNO and STOPS The RXIF bit is set FERR is set zeros are loaded into the receive data register interrupts are generated if appropriate and the RIDLE bit is set If a long break signal has been detected and the receive...

Page 167: ...the USR register followed by a read to the RXR register Noise Error NF Over sampling is used for data recovery to identify valid incoming data and noise If noise is detected within a frame the following will occur The read only noise flag NF in the USR register will be set on the rising edge of the RXIF bit Data will be transferred from the shift register to the RXR register No interrupt will be g...

Page 168: ...EN bit in the UCR2 register An RX pin wake up which is also a UART interrupt source does not have an associated flag but will generate a UART interrupt if the microcontroller is woken up from IDLE0 or SLEEP mode by a falling edge on the RX pin if the WAKE and RIE bits in the UCR2 register are set Note that in the event of an RX wake up interrupt occurring there will be a certain period of delay co...

Page 169: ...e to function If the MCU executes the HALT instruction and switches off the system clock while a transmission is still in progress then the transmission will be paused until the UART clock source derived from the microcontroller is activated In a similar way if the MCU executes the HALT instruction and switches off the system clock while receiving data then the reception of data will likewise be p...

Page 170: ...d A low voltage condition is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will enable the low voltage detector Clearing the bit to zero will switch off the internal low voltage detector circuits As the l...

Page 171: ...he LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi function interrupts providing an alternative means of low voltage detection in addition to polling the LVDO bit The interrupt will only ...

Page 172: ...s upon the device chosen but fall into three categories The first is the INTC0 INTC2 registers which setup the primary interrupts the second is the MFI0 MFI2 registers which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupt trigger edge type Each register contains a number of enable bits to enable or disable individual interrupts as well as inte...

Page 173: ...MF0F CPF INT0F MF0E CPE INT0E EMI INTC1 TB0F ADF MF2F MF1F TB0E ADE MF2E MF1E INTC2 URF SIMF INT1F TB1F URE SIME INT1E TB1E MFI0 T0AF T0PF T0AE T0PE MFI1 T2AF T2PF T1AF T1PF T2AE T2PE T1AE T1PE MFI2 DEF LVF DEE LVE Interrupt Registers List HT66F0185 INTEG Register Bit 7 6 5 4 3 2 1 0 Name INT1S1 INT1S0 INT0S1 INT0S0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 INT1S1 INT...

Page 174: ...interrupt control 0 Disable 1 Enable Bit 0 EMI Global interrupt control 0 Disable 1 Enable INTC0 Register HT66F0185 Bit 7 6 5 4 3 2 1 0 Name MF0F CPF INT0F MF0E CPE INT0E EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 MF0F Multi function 0 interrupt request flag 0 No request 1 Interrupt request Bit 5 CPF Comparator interrupt request flag 0 No request 1 In...

Page 175: ... ADF A D Converter interrupt request flag 0 No request 1 Interrupt request Bit 5 MF2F Multi function 2 interrupt request flag 0 No request 1 Interrupt request Bit 4 MF1F Multi function 1 interrupt request flag 0 No request 1 Interrupt request Bit 3 TB0E Time Base 0 interrupt control 0 Disable 1 Enable Bit 2 ADE A D Converter interrupt control 0 Disable 1 Enable Bit 1 MF2E Multi function 2 interrup...

Page 176: ...d as 0 Bit 6 SIMF SIM interrupt request flag 0 No request 1 Interrupt request Bit 5 INT1F INT1 interrupt request flag 0 No request 1 Interrupt request Bit 4 TB1F Time Base 1 interrupt request flag 0 No request 1 Interrupt request Bit 3 Unimplemented read as 0 Bit 2 SIME SIM interrupt control 0 Disable 1 Enable Bit 1 INT1E INT1 interrupt control 0 Disable 1 Enable Bit 0 TB1E Time Base 1 interrupt c...

Page 177: ...pt request Bit 3 URE UART interrupt control 0 Disable 1 Enable Bit 2 SIME SIM interrupt control 0 Disable 1 Enable Bit 1 INT1E INT1 interrupt control 0 Disable 1 Enable Bit 0 TB1E Time Base 1 interrupt control 0 Disable 1 Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Name T0AF T0PF T0AE T0PE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 T0AF TM0 Comparator A match Interrupt requ...

Page 178: ... HT66F0185 Bit 7 6 5 4 3 2 1 0 Name T2AF T2PF T1AF T1PF T2AE T2PE T1AE T1PE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 T2AF TM2 Comparator A match Interrupt request flag 0 No request 1 Interrupt request Bit 6 T2PF TM2 Comparator P match Interrupt request flag 0 No request 1 Interrupt request Bit 5 T1AF TM1 Comparator A match Interrupt request flag 0 No request 1 Interrupt reques...

Page 179: ...Program Counter which stores the address of the next instruction to be executed will be transferred onto the stack The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector The microcontroller will then fetch its next instruction from this interrupt vector The instruction at this vector will usually be a JMP which will jump to another ...

Page 180: ...LVE EMI 1CH Interr pt Name Req est Fla s Enable Bits Master Enable Vector EMI a to disabled in ISR Priority Hi h Low M F nct 1 MF1F MF1E TM0 P T0PF T0PE TM0 T0 F T0 E Interr pts contained within M lti F nction Interr pts xxE Enable Bits xxF Req est Fla a to reset in ISR Legend xxF Req est Fla no a to reset in ISR EMI 0H D DF DE EMI 4H M F nct MF F MF E Time Base 1 TB1F TB1E TM1 P T1PE TM1 T1 E EEP...

Page 181: ...l interrupt function Comparator Interrupt HT66F0185 The comparator interrupt is controlled by the internal comparator A comparator interrupt request will take place when the comparator interrupt request flag CPF is set a situation that will occur when the comparator output changes state To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI an...

Page 182: ...se happens their respective interrupt request flags TB0F or TB1F will be set To allow the program to branch to their respective interrupt vector addresses the global interrupt enable bit EMI and Time Base enable bits TB0E or TB1E must first be set When the interrupt is enabled the stack is not full and the Time Base overflows a subroutine call to their respective vector locations will take place W...

Page 183: ... address the global interrupt enable bit EMI and the Serial Interface Interrupt enable bit SIME must first be set When the interrupt is enabled the stack is not full and any of the above described situations occurs a subroutine call to the respective SIM Interrupt vector will take place When the Serial Interface Interrupt is serviced the EMI bit will be automatically cleared to disable other inter...

Page 184: ...st first be set When the interrupt is enabled the stack is not full and an EEPROM Write cycle ends a subroutine call to the respective Multi function Interrupt vector will take place When the EEPROM Write Interrupt is serviced the EMI bit will be automatically cleared to disable other interrupts However only the Multi function interrupt request flag will be automatically cleared As the DEF flag wi...

Page 185: ...pt service routine is executed as only the Multi function interrupt request flags MFnF will be automatically cleared the individual request flag for the function needs to be cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately If...

Page 186: ...e hardware programming tools once they are selected they cannot be changed later using the application program All options must be defined for proper system function the details of which are shown in the table No Options 1 High Speed System Oscillator Selection fH HXT or HIRC 2 Low Speed System Oscillator Selection fSUB LXT or LIRC 3 HIRC Frequency Selection fHIRC 8MHz 12MHz or 16MHz Application C...

Page 187: ...le to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one cyc...

Page 188: ...ch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of...

Page 189: ...1Note Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Logical AND immedi...

Page 190: ...outine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDC m Read table current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memory 1Not...

Page 191: ...lator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data...

Page 192: ...TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR WDT2 will have...

Page 193: ... this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Description Data i...

Page 194: ...n m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affected flag s Z OR ...

Page 195: ...ta Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the specified Data Memor...

Page 196: ...BC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC ACC m C Affected...

Page 197: ...he program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remain unchanged As ...

Page 198: ...are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it...

Page 199: ...Data Memory Description The low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation...

Page 200: ...gular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Meterials Information C...

Page 201: ...ensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 504 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 5 BSC C 0 31 0 51 C 12 8 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 202: ...mensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 8 66 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 203: ...ensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 606 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 5 BSC C 0 31 0 51 C 15 4 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 204: ...mensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 8 66 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 205: ...ensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 295 BSC C 0 012 0 020 C 0 705 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 α 0 8 Symbol Dimensions in mm Min Nom Max A 10 30 BSC B 7 50 BSC C 0 31 0 51 C 17 9 BSC D 2 65 E 1 27 BSC F 0 10 0 30 G 0 40 1 27 H 0 20 0 33 α 0 8 ...

Page 206: ...imensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 008 0 012 C 0 390 BSC D 0 069 E 0 025 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 0 BSC B 3 9 BSC C 0 20 0 30 C 9 9 BSC D 1 75 E 0 635 BSC F 0 10 0 25 G 0 41 1 27 H 0 10 0 25 α 0 8 ...

Page 207: ...used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reser...

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