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Rev. 1.40

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Rev. 1.40

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BS67F340/BS67F350/BS67F360/BS67F370

Enhanced Touch A/D Flash MCU with LCD Driver

BS67F340/BS67F350/BS67F360/BS67F370

Enhanced Touch A/D Flash MCU with LCD Driver

Compact Type TM – CTM

Although the simplest form of the TM types, the Compact TM type still contains three operating
modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The
Compact TM can also be controlled with an external input pin and can drive two external output pin.

Device

CTM Core

CTM Input Pin

CTM Output Pin

Note

BS�7F340

BS�7F3�0

BS�7F3�0

BS�7F370

10-�it CTM

(CTM0� CTM1)

CTCK0� CTCK1

CTP0� CTP0B

CTP1� CTP1B

n=0 ~ 1

f

SYS

f

SYS

/4

f

H

/64

f

H

/16

f

SUB

CTCKn

000
001
010
011
100
101
110
111

CTnCK�~CTnCK0

10-�it Count-up Counte�

3-�it Co�pa�ato� P

CCRP

�7~�9

�0~�9

10-�it Co�pa�ato� A

CTnON

CTnPAU

Co�pa�ato� A Mat�h

Co�pa�ato� P Mat�h

Counte� Clea�

0
1

Output

Cont�ol

Pola�ity

Cont�ol

Pin

Cont�ol

CTPn

CTnOC

CTnM1� CTnM0

CTnIO1� CTnIO0

CTMnAF Inte��upt

CTMnPF Inte��upt

CTnPOL

PxSn

CCRA

CTnCCLR

f

SUB

CTPnB

Compact Type TM Block Diagram – n=0 or 1

Compact TM Operation

The Compact TM core is a 10-bit count-up counter which is driven by a user selectable internal or
external clock source. There are also two internal comparators with the names, Comparator A and
Comparator P. These comparators will compare the value in the counter with CCRP and CCRA
registers. The CCRP is three-bit wide whose value is compared with the highest three bits in the
counter while the CCRA is ten-bit wide and therefore compares with all counter bits.
The only way of changing the value of the 10-bit counter using the application program, is to
clear the counter by changing the CTnON bit from low to high. The counter will also be cleared
automatically by a counter overflow or a compare match with one of its associated comparators.
When these conditions occur, a TM interrupt signal will also usually be generated. The Compact
Type TM can operate in a number of different operational modes, can be driven by different clock
sources including an input pin and can also control an output pin. All operating setup conditions are
selected using relevant internal registers.

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Summary of Contents for BS67F340

Page 1: ...Enhanced Touch A D Flash MCU with LCD Driver BS67F340 BS67F350 BS67F360 BS67F370 Revision V1 40 Date December 15 2016 ...

Page 2: ...ectrical Characteristics 40 LVD LVR Electrical Characteristics 40 LCD Driver Electrical Characteristics 41 Touch Key Electrical Characteristics 41 Power on Reset Characteristics 43 System Architecture 44 Clocking and Pipelining 44 Program Counter 45 Stack 46 Arithmetic and Logic Unit ALU 46 Flash Program Memory 47 Structure 47 Special Vectors 48 Look up Table 48 Table Program Example 48 In Circuit...

Page 3: ...OM 76 Writing Data to the EEPROM 76 Write Protection 76 EEPROM Interrupt 76 Programming Considerations 77 Oscillators 78 Oscillator Overview 78 System Clock Configurations 78 External Crystal Ceramic Oscillator HXT 79 Internal High Speed RC Oscillator HIRC 80 External 32 768 kHz Crystal Oscillator LXT 80 Internal 32kHz Oscillator LIRC 81 Operating Modes and System Clocks 82 System Clocks 82 System...

Page 4: ... 126 Compact Type TM Register Description 127 Compact Type TM Operation Modes 131 Standard Type TM STM 137 Standard TM Operation 137 Standard Type TM Register Description 138 Standard Type TM Operation Modes 142 Periodic Type TM PTM 152 Periodic TM Operation 152 Periodic Type TM Register Description 153 Periodic Type TM Operation Modes 157 Analog to Digital Converter 166 A D Overview 166 Registers...

Page 5: ...d Biasing 215 LCD Reset Function 216 LCD Driver Output 217 Programming Considerations 220 Touch Key Function 220 Touch Key Structure 220 Touch Key Register Definition 223 Touch Key Operation 230 Touch Key Interrupt 237 Progrsmming Considerations 237 Low Voltage Detector LVD 238 LVD Register 238 LVD Operation 239 Interrupts 240 Interrupt Registers 240 Interrupt Operation 247 External Interrupt 248 ...

Page 6: ...erations 255 Logical and Rotate Operation 256 Branches and Control Transfer 256 Bit Operations 256 Table Read Operations 256 Other Operations 256 Instruction Set Summary 257 Table Conventions 257 Extended Instruction Set 259 Instruction Definition 261 Extended Instruction Definition 270 Package Information 277 48 pin LQFP 7mm 7mm Outline Dimensions 278 64 pin LQFP 7mm 7mm Outline Dimensions 279 80...

Page 7: ...own and wake up functions to reduce power consumption Oscillator type External High Speed Crystal HXT Internal High Speed RC HIRC External 32 768kHz Crystal LXT Internal 32kHz RC LIRC Fully integrated internal 8 12 16MHz oscillator requires no external components Multi mode operation NORMAL SLOW IDLE and SLEEP All instructions executed in one to three instruction cycles Table read instructions 115...

Page 8: ...ly duplex Universal Asynchronous Receiver and Transmitter Interface UART LCD driver funciton with 1 3 bias R type C type bias Fully integrated up to 36 touch key functions require no external components Dual Time Base functions for generation of fixed time interrupt signals 8 channel 12 bit resolution A D converter Temperature Sensor In Application Programming function IAP Low voltage reset functi...

Page 9: ...ources gives users the ability to optimise microcontroller operation and minimise power consumption Easy communication with the outside world is provided using the internal UART I2 C and SPI interfaces while the inclusion of flexible I O programming features Timer modules and many other features further enhance device functionality and flexibility The touch key devices will find excellent use in a...

Page 10: ...40 BS67V340 48 LQFP A PB4 PTPB PTPI AN4 KEY1 PB5 STCK AN5 KEY2 PB6 PTCK AN6 KEY3 PB7 INT1 AN7 KEY4 SEG0 PC0 KEY5 SEG1 PC1 KEY6 SEG2 PC2 KEY7 SEG3 PC3 KEY8 SEG4 PD4 KEY9 SEG5 PD5 KEY10 SEG6 PD6 KEY11 SEG7 PA7 KEY12 13 14 1 1 17 18 19 0 1 3 4 1 3 4 7 8 9 10 11 1 3 3 34 33 3 31 30 9 8 7 37 38 39 40 41 4 43 44 4 4 47 48 V1 PA1 CTP0 V2 PA5 CTP0B C1 PA6 CTCK0 INT0 C2 COM0 COM1 COM COM3 SEG 3 SEG SEG 1 S...

Page 11: ...PD6 KEY19 SEG7 PA7 KEY20 13 14 1 1 17 18 19 0 1 3 4 1 3 4 7 8 9 10 11 1 3 3 34 33 3 31 30 9 8 7 37 38 39 40 41 4 43 44 4 4 47 48 V1 PA1 CTP0 V2 PA5 CTP0B C1 PA6 CTCK0 INT0 C2 COM0 COM1 COM COM3 SEG 7 SEG SEG SEG 4 SEG8 PE0 SEG9 PE1 OSC1 SEG10 PE2 STP STPI OSC2 SEG11 PE3 STPB STPI SEG12 PE4 SEG13 PE5 CTCK1 SEG14 PE6 CTP1 SEG15 PE7 CTP1B SEG 0 SEG 1 SEG SEG 3 PB3 RX AN3 PB2 PTP PTPI TX AN2 PB1 SCK S...

Page 12: ...EY15 SEG0 PD0 KEY13 PC1 KEY6 PA6 CTCK0 INT0 C2 COM1 COM COM3 1 3 4 7 8 9 10 11 1 13 0 1 3 4 7 8 0 1 3 4 930313 3 4 7 8 9 14 1 1 43 44 4 4 47 48 3 37 38 39 40 41 4 33 34 3 171819 49 0 1 SEG12 PE4 SEG8 PE0 SEG9 PE1 OSC1 SEG10 PE2 STP STPI OSC2 SEG11 PE3 STPB STPI SEG13 PE5 CTCK1 SEG14 PE6 CTP1 SEG15 PE7 CTP1B PB7 INT1 AN7 KEY4 PB6 PTCK AN6 KEY3 PB5 STCK AN5 KEY2 PB4 PTPB PTPI AN4 KEY1 SEG 1 SEG SEG ...

Page 13: ... 1 17 18 19 0 1 3 4 1 3 4 7 8 9 10 11 1 3 3 34 33 3 31 30 9 8 7 37 38 39 40 41 4 43 44 4 4 47 48 V1 PA1 CTP0 V2 PA5 CTP0B C1 PA6 CTCK0 INT0 C2 COM0 COM1 COM COM3 SEG3 SEG34 SEG33 SEG3 SEG16 PE0 KEY21 SEG17 PE1 KEY22 SEG18 PE2 STP STPI KEY23 SEG19 PE3 STPB STPI KEY24 SEG20 PE4 KEY25 SEG21 PE5 CTCK1 KEY26 SEG22 PE6 CTP1 KEY27 SEG23 PE7 CTP1B KEY28 SEG28 PF0 OSC1 SEG29 PF1 OSC2 SEG30 PF2 SEG31 PF3 PB...

Page 14: ...PC5 KEY10 SEG4 PC4 KEY9 SEG3 PC3 KEY8 SEG2 PC2 KEY7 SEG0 PC0 KEY5 PB7 INT1 AN7 KEY4 PB6 PTCK AN6 KEY3 PB5 STCK AN5 KEY2 PB4 PTPB PTPI AN4 KEY1 PB3 RX AN3 SEG33 SEG34 SEG3 SEG3 SEG37 SEG38 SEG39 SEG29 PF1 OSC2 SEG30 PF2 SEG31 PF3 SEG3 PA1 CTP0 V2 V1 VDD PA2 SCS ICPCK OCDSCK PA0 SDO ICPDA OCDSDA VSS PA3 SCS XT1 PA4 SDO XT2 VMAX PLCD PA5 CTP0B C1 COM0 SEG 7 SEG9 PD1 KEY14 SEG10 PD2 KEY15 SEG8 PD0 KEY...

Page 15: ... 1 17 18 19 0 1 3 4 1 3 4 7 8 9 10 11 1 3 3 34 33 3 31 30 9 8 7 37 38 39 40 41 4 43 44 4 4 47 48 V1 PA1 CTP0 V2 PA5 CTP0B C1 PA6 CTCK0 INT0 C2 COM0 COM1 COM COM3 SEG3 SEG34 SEG33 SEG3 SEG16 PE0 KEY21 SEG17 PE1 KEY22 SEG18 PE2 STP STPI KEY23 SEG19 PE3 STPB STPI KEY24 SEG20 PE4 KEY25 SEG21 PE5 CTCK1 KEY26 SEG22 PE6 CTP1 KEY27 SEG23 PE7 CTP1B KEY28 SEG28 PF0 OSC1 SEG29 PF1 OSC2 SEG30 PF2 SEG31 PF3 PB...

Page 16: ...9 SEG3 PC3 KEY8 SEG2 PC2 KEY7 SEG0 PC0 KEY5 PB7 INT1 AN7 KEY4 PB6 PTCK AN6 KEY3 PB5 STCK AN5 KEY2 PB4 PTPB PTPI AN4 KEY1 PB3 RX AN3 SEG33 SEG34 SEG3 SEG3 SEG37 SEG38 SEG39 SEG29 PF1 OSC2 SEG30 PF2 SEG31 PF3 SEG3 PA1 CTP0 V2 V1 VDD PA2 SCS ICPCK OCDSCK PA0 SDO ICPDA OCDSDA VSS PA3 SCS XT1 PA4 SDO XT2 VMAX PLCD PA5 CTP0B C1 COM0 SEG27 PG3 KEY32 SEG9 PD1 KEY14 SEG10 PD2 KEY15 SEG8 PD0 KEY13 PB1 SCK S...

Page 17: ...OCDSCK PA0 SDO ICPDAOCDSDA VSS PA3 SCS XT1 PA4 SDO XT2 VMAX PLCD PA5 CTP0B C1 COM0 SEG27 PG3 KEY32 SEG9 PD1 KEY14 SEG10 PD2 KEY15 SEG8 PD0 KEY13 PB1 SCK SCL AN1 PB0 VREF SDI SDA AN0 SEG1 PC1 KEY6 PA6 CTCK0 INT0 C2 COM1 COM COM3 SEG26 PG2 KEY31 SEG25 PG1 KEY30 SEG24 PG0 KEY29 SEG28 PF0 OSC1 47 4 4 44 43 4 41 1 3 4 7 8 9 10 11 1 13 14 1 1 17 18 19 0 1 3 4 7 8 9 30 31 3 33 34 3 3 3738 39 40 80 79 78 ...

Page 18: ... output ICPDA ST CMOS ICP Data Address pin OCDSDA ST CMOS OCDS Data Address pin for EV chip only PA1 CTP0 V2 PA1 PAWU PAPU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up CTP0 PAS0 CMOS CTM0 output V2 PAS0 AN LCD voltage pump PA2 SCS ICPCK OCDSCK PA2 PAWU PAPU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up SCS PAS0 IFS ST CMOS SPI slave select ICPCK ST ...

Page 19: ...e input TX PBS0 CMOS UART TX serial data output PTP PBS0 CMOS PTM output AN2 PBS0 AN A D Converter analog input PB3 RX AN3 PB3 PBPU PBS0 ST CMOS General purpose I O Register enabled pull up RX PBS0 ST UART RX serial data input AN3 PBS0 AN A D Converter analog input PB4 PTPI PTPB KEY1 AN4 PB4 PBPU PBS1 ST CMOS General purpose I O Register enabled pull up PTPI PBS1 IFS ST PTM capture input PTPB PBS1...

Page 20: ...PDS1 AN Touch key input SEG4 PDS1 AN LCD segment output PD5 KEY10 SEG5 PD5 PDPU PDS1 ST CMOS General purpose I O Register enabled pull up KEY10 PDS1 AN Touch key input SEG5 PDS1 AN LCD segment output PD6 KEY11 SEG6 PD6 PDPU PDS1 ST CMOS General purpose I O Register enabled pull up KEY11 PDS1 AN Touch key input SEG6 PDS1 AN LCD segment output PE0 SEG12 PE0 PEPU PES0 ST CMOS General purpose I O Regi...

Page 21: ...MOS CTM1 output KEY15 PES1 AN Touch key input SEG10 PES1 AN LCD segment output PE7 CTP1B KEY16 SEG11 PE7 PEPU PES1 ST CMOS General purpose I O Register enabled pull up CTP1B PES1 CMOS CTM1 inverted output KEY16 PES1 AN Touch key input SEG11 PES1 AN LCD segment output SEG16 SEG23 SEGn LCDC0 AN LCD segment output COM0 COM3 COMn LCDC0 AN LCD common output V1 V1 AO LCD voltage pump PLCD PLCD PWR LCD p...

Page 22: ...ck pin OCDSCK ST OCDS Clock pin for EV chip only PA3 SCS XT1 PA3 PAWU PAPU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up SCS PAS0 IFS ST CMOS SPI slave select XT1 PAS0 LXT LXT oscillator pin PA4 SDO XT2 PA4 PAWU PAPU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up SDO PAS1 CMOS SPI data output XT2 PAS1 LXT LXT oscillator pin PA5 CTP0B C1 PA5 PAWU PAPU ...

Page 23: ...BS0 ST CMOS General purpose I O Register enabled pull up RX PBS0 ST UART RX serial data input AN3 PBS0 AN A D Converter analog input PB4 PTPI PTPB KEY1 AN4 PB4 PBPU PBS1 ST CMOS General purpose I O Register enabled pull up PTPI PBS1 IFS ST PTM capture input PTPB PBS1 CMOS PTM inverted output KEY1 PBS1 AN Touch key input AN4 PBS1 AN A D Converter analog input PB5 STCK KEY2 AN5 PB5 PBPU PBS1 ST CMOS...

Page 24: ...abled pull up KEY12 PCS1 AN Touch key input PD0 KEY13 SEG0 PD0 PDPU PDS0 ST CMOS General purpose I O Register enabled pull up KEY13 PDS0 AN Touch key input SEG0 PDS0 AN LCD segment output PD1 KEY14 SEG1 PD1 PDPU PDS0 ST CMOS General purpose I O Register enabled pull up KEY14 PDS0 AN Touch key input SEG1 PDS0 AN LCD segment output PD2 KEY15 SEG2 PD2 PDPU PDS0 ST CMOS General purpose I O Register en...

Page 25: ...ST CMOS General purpose I O Register enabled pull up SEG12 PES1 AN LCD segment output PE5 CTCK1 SEG13 PE5 PEPU PES1 ST CMOS General purpose I O Register enabled pull up CTCK1 PES1 ST CTM1 clock input SEG13 PES1 AN LCD segment output PE6 CTP1 SEG14 PE6 PEPU PES1 ST CMOS General purpose I O Register enabled pull up CTP1 PES1 CMOS CTM1 output SEG14 PES1 AN LCD segment output PE7 CTP1B SEG15 PE7 PEPU ...

Page 26: ...k pin OCDSCK ST OCDS Clock pin for EV chip only PA3 SCS XT1 PA3 PAWU PAPU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up SCS PAS0 IFS ST CMOS SPI slave select XT1 PAS0 LXT LXT oscillator pin PA4 SDO XT2 PA4 PAWU PAPU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up SDO PAS1 CMOS SPI data output XT2 PAS1 LXT LXT oscillator pin PA5 CTP0B C1 PA5 PAWU PAPU P...

Page 27: ... purpose I O Register enabled pull up RX PBS0 ST UART RX serial data input AN3 PBS0 AN A D Converter analog input PB4 PTPI PTPB KEY1 AN4 PB4 PBPU PBS1 ST CMOS General purpose I O Register enabled pull up PTPI PBS1 IFS ST PTM capture input PTPB PBS1 CMOS PTM inverted output KEY1 PBS1 AN Touch key input AN4 PBS1 AN A D Converter analog input PB5 STCK KEY2 AN5 PB5 PBPU PBS1 ST CMOS General purpose I ...

Page 28: ...CS1 AN LCD segment output PC6 KEY11 SEG6 PC6 PCPU PCS1 ST CMOS General purpose I O Register enabled pull up KEY11 PCS1 AN Touch key input SEG6 PCS1 AN LCD segment output PC7 KEY12 SEG7 PC7 PCPU PCS1 ST CMOS General purpose I O Register enabled pull up KEY12 PCS1 AN Touch key input SEG7 PCS1 AN LCD segment output PD0 KEY13 SEG8 PD0 PDPU PDS0 ST CMOS General purpose I O Register enabled pull up KEY1...

Page 29: ...S0 IFS ST STM capture input STP PES0 CMOS STM output KEY23 PES0 AN Touch key input SEG18 PES0 AN LCD segment output PE3 STPI STPB KEY24 SEG19 PE3 PEPU PES0 ST CMOS General purpose I O Register enabled pull up STPI PES0 IFS ST STM capture input STPB PES0 CMOS STM inverted output KEY24 PES0 AN Touch key input SEG19 PES0 AN LCD segment output PE4 KEY25 SEG20 PE4 PEPU PES1 ST CMOS General purpose I O ...

Page 30: ...e I O Register enabled pull up SEG30 PFS0 AN LCD segment output PF3 SEG31 PF3 PFPU PFS0 ST CMOS General purpose I O Register enabled pull up SEG31 PFS0 AN LCD segment output SEG24 SEG27 SEG32 SEG39 SEGn LCDC0 AN LCD segment output COM0 COM3 COMn LCDC0 AN LCD common output V1 V1 AO LCD voltage pump PLCD PLCD PWR LCD power supply VMAX VMAX PWR IC maximum voltage connected to VDD PLCD or V1 VDD VDD P...

Page 31: ...k pin OCDSCK ST OCDS Clock pin for EV chip only PA3 SCS XT1 PA3 PAWU PAPU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up SCS PAS0 IFS ST CMOS SPI slave select XT1 PAS0 LXT LXT oscillator pin PA4 SDO XT2 PA4 PAWU PAPU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up SDO PAS1 CMOS SPI data output XT2 PAS1 LXT LXT oscillator pin PA5 CTP0B C1 PA5 PAWU PAPU P...

Page 32: ... purpose I O Register enabled pull up RX PBS0 ST UART RX serial data input AN3 PBS0 AN A D Converter analog input PB4 PTPI PTPB KEY1 AN4 PB4 PBPU PBS1 ST CMOS General purpose I O Register enabled pull up PTPI PBS1 IFS ST PTM capture input PTPB PBS1 CMOS PTM inverted output KEY1 PBS1 AN Touch key input AN4 PBS1 AN A D Converter analog input PB5 STCK KEY2 AN5 PB5 PBPU PBS1 ST CMOS General purpose I ...

Page 33: ...CS1 AN LCD segment output PC6 KEY11 SEG6 PC6 PCPU PCS1 ST CMOS General purpose I O Register enabled pull up KEY11 PCS1 AN Touch key input SEG6 PCS1 AN LCD segment output PC7 KEY12 SEG7 PC7 PCPU PCS1 ST CMOS General purpose I O Register enabled pull up KEY12 PCS1 AN Touch key input SEG7 PCS1 AN LCD segment output PD0 KEY13 SEG8 PD0 PDPU PDS0 ST CMOS General purpose I O Register enabled pull up KEY1...

Page 34: ...S0 IFS ST STM capture input STP PES0 CMOS STM output KEY23 PES0 AN Touch key input SEG18 PES0 AN LCD segment output PE3 STPI STPB KEY24 SEG19 PE3 PEPU PES0 ST CMOS General purpose I O Register enabled pull up STPI PES0 IFS ST STM capture input STPB PES0 CMOS STM inverted output KEY24 PES0 AN Touch key input SEG19 PES0 AN LCD segment output PE4 KEY25 SEG20 PE4 PEPU PES1 ST CMOS General purpose I O ...

Page 35: ...GS0 AN LCD segment output KEY30 PGS0 AN Touch key input PG2 SEG26 KEY31 PG2 PGPU PGS0 ST CMOS General purpose I O Register enabled pull up SEG26 PGS0 AN LCD segment output KEY31 PGS0 AN Touch key input PG3 SEG27 KEY32 PG3 PGPU PGS0 ST CMOS General purpose I O Register enabled pull up SEG27 PGS0 AN LCD segment output KEY32 PGS0 AN Touch key input PG4 KEY33 PG4 PGPU PGS1 ST CMOS General purpose I O ...

Page 36: ...tage pump PLCD PLCD PWR LCD power supply VMAX VMAX PWR IC maximum voltage connected to VDD PLCD or V1 VDD VDD1 VDD PWR Positive power supply VSS VSS1 VSS PWR Negative power supply ground NC No Connection Legend I T Input type O T Output type OPT Optional by register option PWR Power ST Schmitt Trigger input AN Analog signal CMOS CMOS output NMOS NMOS output HXT High frequency crystal oscillator LX...

Page 37: ...erals off 1 2 1 8 mA 5V 2 4 3 6 mA 5V fSYS fH 16MHz no load all peripherals off 3 2 4 8 mA Operating Current LXT 3V fSYS fSUB fLXT 32 768kHz No load all peripherals off 10 20 μA 5V 30 50 μA Operating Current LIRC 3V fSYS fSUB fLIRC 32kHz No load all peripherals off 10 20 μA 5V 30 50 μA ISTB Standby Current IDLE0 Mode 3V fSYS off fSUB on No load all peripherals off WDT enabled 1 3 3 0 μA 5V 2 4 5 0...

Page 38: ...or HIRC 12MHz trim at VDD 5V 5V Ta 25 C 2 12 2 MHz 5V 0 1V Ta 0 C to 70 C 5 12 5 MHz 2 7V 5 5V Ta 0 C to 70 C 7 12 7 MHz 2 7V 5 5V Ta 40 C to 85 C 10 12 10 MHz 5V Ta 25 C 20 8 20 MHz 5V Ta 25 C 20 16 20 MHz fLIRC Low Speed Internal RC Oscillator LIRC 5V Ta 25 C 10 32 10 kHz 2 2V 5 5V Ta 40 C to 85 C 40 32 40 kHz tTPI CTPnI STPI PTPI Pin Minimum Input Pulse Width 0 3 μs tTCK CTCKn STCK PTCK Pin Min...

Page 39: ...herwise specified Symbol Parameter Test Conditions Min Max Unit VDD Conditions VDD Operating Voltage 2 7 5 5 V VADI Input Voltage 0 VREF V VREF Reference Voltage 2 VDD V DNL Differential Non linearity 3V VREF VDD tADCK 0 5μs or 10μs 3 LSB 5V INL Integral Non linearity 3V VREF VDD tADCK 0 5μs or 10μs 4 LSB 5V IADC Additional Current Consumption for A D Converter Enable 3V No load tADCK 0 5μs 1 0 2 ...

Page 40: ...ristics Ta 25 C Symbol Parameter Test Conditions Min Max Unit VDD Conditions VLVR Low Voltage Reset Voltage LVR Enable voltage select 2 1V 5 2 1 5 V LVR Enable voltage select 2 55V 2 55 LVR Enable voltage select 3 15V 3 15 LVR Enable voltage select 3 8V 3 8 VLVD Low Voltage Detector Voltage LVD Enable voltage select 2 0V 5 2 0 5 V LVD Enable voltage select 2 2V 2 2 LVD Enable voltage select 2 4V 2...

Page 41: ...A ILCDOH LCD Common and Segment Source Current 3V VOL 0 9VDD 80 160 μA 5V 180 360 μA Touch Key Electrical Characteristics Ta 25 C Touch Key RC Oscillator 500kHz Mode Selected Symbol Parameter Test Conditions Min Max Unit VDD Conditions IKEYOSC Only Sensor KEY Oscillator Operating Current 3V fSENOSC 500kHz 30 60 μA 5V 60 120 IREFOSC Only Reference Oscillator Operating Current 3V fREFOSC 500kHz MnTS...

Page 42: ...qual to 1000kHz 2 fREFOSC 1000kHz Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 1000kHz Touch Key RC Oscillator 1500kHz Mode Selected Symbol Parameter Test Conditions Min Max Unit VDD Conditions IKEYOSC Only Sensor KEY Oscillator Operating Current 3V fSENOSC 1500kHz 60 120 μA 5V 120 240 IREFOSC Only Reference Oscillator Operating Cu...

Page 43: ...C 2000kHz 4 8 20 pF 5V 5 10 20 pF fKEYOSC Sensor KEY Oscillator Operating Frequency 3V CEXT 3 4 5 6 7 8 9 50pF 150 2000 4000 kHz 5V 150 2000 4000 kHz fREFOSC Reference Oscillator Operating Frequency 3V CEXT 3 4 5 6 7 8 9 50pF 150 2000 4000 kHz 5V 150 2000 4000 kHz Note 1 fSENOSC 2000kHz Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 2000kHz 2 fREFOSC 2...

Page 44: ...ovide a functional I O and A D control system with maximum reliability and flexibility This makes these devices suitable for low cost high volume production for controller applications Clocking and Pipelining The main system clock derived from either a HXT LXT HIRC or LIRC oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Program Counter is incremented at the...

Page 45: ...terrupt or reset etc the microcontroller manages program control by loading the required address into the Program Counter For conditional skip instructions once the condition has been met the next instruction which has already been fetched during the present instruction execution is discarded and a dummy cycle takes its place while the correct instruction is obtained Device Program Counter High By...

Page 46: ...k overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is overflow the first Program Counter save in the stack will be lost Sta k Pointe Sta k Level Sta k Level 1 Sta k Level 3 Stack Level N P og a Me o y P og a Counte Botto of Sta k Top of Sta k Note N 8 for BS67F340 BS67F350 N 12 for BS67F360 N 16 for BS67F370 Arithmetic and Logi...

Page 47: ...ng and updating Device Capacity Banks BS67F340 4K 16 BS67F350 8K 16 BS67F360 16K 16 0 1 BS67F370 32K 16 0 3 Structure The Program Memory has a capacity of 4K 16 to 16K 16 bits The Program Memory is addressed by the Program Counter and also contains data table information and interrupt entries Table data which can be setup in any location within the Program Memory is addressed by a separate table p...

Page 48: ...e c t e d R e g i s t e r H i g h B y t e L o w B y t e L a s t p a g e o r T B H P R e g i s t e r T B L P R e g i s t e r D a t a A d d r e s s 1 6 b i t s Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device This example uses raw table data located in the last page which is stored there using the ORG statement The val...

Page 49: ...evice As an additional convenience Holtek has provided a means of programming the microcontroller in circuit using a 4 pin interface This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un programmed microcontroller and then programming or upgrading the program at a later stage This enables product manufacturers to easily keep their m...

Page 50: ... the EV chip device for debugging the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no effect in the EV chip However the two OCDS pins which are pin shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP For more detailed OCDS information refer to the corresponding document named Holtek e Link for 8 bit...

Page 51: ...FC2 control registers are located at the address of 50H 52H in Data Memory sector 0 the desired value ranged from 50H to 52H must first be written into the MP1L or MP2L Memory Pointer low byte and the value 00H must also be written into the MP1H or MP2H Memory Pointer high byte Register Name Bit 7 6 5 4 3 2 1 0 FC0 CFWEN FMOD2 FMOD1 FMOD0 FWPEN FWT FRDEN FRD FC1 D7 D6 D5 D4 D3 D2 D1 D0 FC2 BS67F35...

Page 52: ...0 FWEN mode Flash memory Write function Enabled mode 111 Reserved When these bits are set to 001 the Block erase mode is selected for BS67F340 while the Page erase mode is selected for BS67F350 BS67F360 BS67F370 Bit 3 FWPEN Flash memory Write Procedure Enable control 0 Disable 1 Enable When this bit is set to 1 and the FMOD field is set to 110 the IAP controller will execute the Flash memory write...

Page 53: ...ontrol 0 Do not initiate Write Buffer Clear process or Write Buffer Clear process is completed 1 Initiate Write Buffer Clear process This bit is set by software and cleared by hardware when the Write Buffer Clear process is completed FARL Register Bit 7 6 5 4 3 2 1 0 Name A7 A6 A5 A4 A3 A2 A1 A0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 Flash Memory Address bit 7 bit 0 FARH R...

Page 54: ...bit 8 FD0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 The first Flash Memory data bit 7 bit 0 FD0H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 The first Flash Memory data bit 15 bit 8 FD1L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3...

Page 55: ... 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 The third Flash Memory data bit 15 bit 8 FD3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 The fourth Flash Memory data bit 7 bit 0 FD3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W ...

Page 56: ...a is incorrect the Flash memory write operation will not be enabled and users must again repeat the above procedure Then the FWPEN bit will automatically be cleared to 0 by hardware 6 If the pattern data is correct before the counter overflows the Flash memory write operation will be enabled and the FWPEN bit will automatically be cleared to 0 by hardware The CFWEN bit will also be set to 1 by har...

Page 57: ... FARH register and the content in the FARL register is not used to specify the block address For the BS67F350 and BS67F360 370 devices the number of the page erase operation is 32 and 64 words per page respectively the available page erase address is specified by FARH register and the content of FARL 7 5 and FARL 7 6 bit field respectively Erase Block FARH 3 0 FARL 7 0 0 0000 xxxx xxxx 1 0001 xxxx...

Page 58: ...6 0000 1111 110 x xxxx 127 0000 1111 111 x xxxx 128 0001 0000 000 x xxxx 129 0001 0000 001 x xxxx 254 0001 1111 110 x xxxx 255 0001 1111 111 x xxxx x don t care BS67F350 Erase Page Number and Selection Erase Page FARH FARL 7 6 FARL 5 0 0 0000 0000 00 xx xxxx 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx 5 0000 0001 01 xx xxxx 126 0001 1111 10 xx xxxx 1...

Page 59: ... 1 0000 0000 01 xx xxxx 2 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx 5 0000 0001 01 xx xxxx 126 0001 1111 10 xx xxxx 127 0001 1111 11 xx xxxx 128 0010 0000 00 xx xxxx 129 0010 0000 01 xx xxxx 254 0011 1111 10 xx xxxx 255 0011 1111 11 xx xxxx 510 0111 1111 10 xx xxxx 511 0111 1111 11 xx xxxx x don t care BS67F370 Erase Page Number and Selection ...

Page 60: ...7F370 Enhanced Touch A D Flash MCU with LCD Driver Read Flash Me o y Clear FRDEN bit END Read Finish Yes No Set FMOD 0 011 FRDEN 1 Set Flash Add ess egiste s FARH xxh FARL xxh FRD 0 Yes No Read data value FD0L xxh FD0H xxh Set FRD 1 Read Flash Memory Procedure ...

Page 61: ...P o edu e Set FWT 1 FWT 0 Yes No Set Block Erase address FARH FARL Set FMOD 0 001 FWT 1 Sele t Blo k E ase ode Initiate w ite ope ation FWT 0 Yes No END W ite Finish Yes No Clear CFWEN 0 Set FMOD 0 000 Sele t W ite Flash Mode Set W ite sta ting address FARH FARL W ite data to data egiste FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H Write Flash Memory Procedure BS67F340 ...

Page 62: ...ge Erase address FARH FARL Set FMOD 0 001 FWT 1 Sele t Page E ase ode Initiate w ite ope ation FWT 0 Yes No END W ite Finish Yes No Clear CFWEN 0 Set FMOD 0 000 Sele t W ite Flash Mode Set Write starting address FARH FARL Write data to data register FD0L FD0H Page data W ite finish Yes No Write Flash Memory Procedure BS67F350 BS67F360 BS67F370 Note When the FWT or FRD bit is set to 1 the MCU is st...

Page 63: ...rs all of which are implemented in 8 bit wide Memory Each of the Data Memory sectors is categorized into two types the Special Purpose Data Memory and the General Purpose Data Memory The address range of the Special Purpose Data Memory for the device is from 00H to 7FH The General Purpose Data Memory address range is from 80H to FFH except the LCD Display and Touch Key Module Data Memory The LCD D...

Page 64: ...stead of using the indirect addressing access The main difference between standard instructions and extended instructions is that the data memory address m in the extended instructions can be from 10 bits to 12 bits depending upon which device is selected the high byte indicates a sector and the low byte indicates a specific address General Purpose Data Memory All microcontroller programs require ...

Page 65: ...4H 35H 36H 37H 3BH 39H 3AH 71H 72H 73H 74H 75H 76H 7BH PBC PBPU PB 3DH 3FH 3EH 7FH MP1H IAR2 MP2L MP2H PSCR0 TB1C SCC HXTC LXTC RSTC PCC PCPU PC 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH SIMTOC SIMC0 SIMC1 SIMD SIMA SIMC2 FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H Sector 1 HIRCC RSTFC INTC1 INTC2 PD PDC PDPU ADRL ADCR0 ADRH ADCR1 PSCR1 LCDC0 LCDC1 PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRP...

Page 66: ...73H 74H 75H 76H 7BH PBC PBPU PB 3DH 3FH 3EH 7FH MP1H IAR2 MP2L MP2H PSCR0 TB1C SCC HXTC LXTC RSTC PCC PCPU PC 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH SIMTOC SIMC0 SIMC1 SIMD SIMA SIMC2 FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H Sector 1 HIRCC RSTFC INTC1 INTC2 PD PDC PDPU ADRL ADCR0 ADRH ADCR1 PSCR1 LCDC0 LCDC1 PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH STMC0 STMC1 STMDL STMDH ST...

Page 67: ...2H PSCR0 TB1C SCC HXTC LXTC RSTC PCC PCPU PC 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH SIMTOC SIMC0 SIMC1 SIMD SIMA SIMC2 FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H Sector 1 HIRCC RSTFC INTC1 INTC2 PD PDC PDPU ADRL ADCR0 ADRH ADCR1 PSCR1 LCDC0 LCDC1 PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TS...

Page 68: ...MTOC SIMC0 SIMC1 SIMD SIMA SIMC2 FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FD2L FD2H FD3L FD3H Sector 1 HIRCC RSTFC INTC1 INTC2 PD PDC PDPU ADRL ADCR0 ADRH ADCR1 PSCR1 LCDC0 LCDC1 PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC2 TSC3 PE PEC PEPU 77H 78H USR UCR1 UCR2 TXR_RXR BRG 79H 7AH TKTMR TKC0 TK16D...

Page 69: ...Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation Memory Pointers MP0 MP1H MP1L MP2H MP2L Five Memory Pointers known as MP0 MP1L MP1H MP2L and MP2H are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with wh...

Page 70: ...y MP1L inc mp1l increment memory pointer MP1L sdz block check if last memory location has been cleared jmp loop continue The important point to note here is that in the example shown above no reference is made to specific RAM addresses Direct Addressing Program Example using extended instructions data section data temp db code section at 0 code org 00h start lmov a m move m data to acc lsub a m 1 ...

Page 71: ...3 Accumulator ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU The Accumulator is the place where all intermediate results from the ALU are stored Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition subtraction shift etc to the Data Memory resu...

Page 72: ...power up a WDT time out or by executing the CLR WDT or HALT instruction The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power up The Z OV AC C SC and CZ flags generally reflect the status of the latest operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation ot...

Page 73: ...atchdog Time out flag 0 After power up ow executing the CLR WDT or HALT instruction 1 A watchdog time out occurred Bit 4 PDF Power down flag 0 After power up ow executing the CLR WDT instruction 1 By executing the HALT instructin Bit 3 OV Overflow flag 0 No overflow 1 An operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa Bit 2 Z Zero ...

Page 74: ...le in the same way as the other types of memory Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1 EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory These are the address register EEA the data register EED and a single control regis...

Page 75: ...y the application program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN has not first been set high Bit 1 RDEN Data EEPROM read enable 0 Disable 1 Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out ...

Page 76: ...ata will have been written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR bit will be automatically cleared to zero by the microcontroller informing the user that the data has been written to the EEPROM The application program can therefore poll t...

Page 77: ...that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete Otherwise the EEPROM read or write operation will fail Programming Example Reading data from the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer low byte MP1L MOV MP1L A MP1L points to EEC register MOV A 01H setup Memory Pointe...

Page 78: ...y to optimize the performance power ratio a feature especially important in power sensitive portable applications Type Name Frequency Pins External High Speed Crystal HXT 400kHz 16MHz OSC1 OSC2 Internal High Speed RC HIRC 8 12 16MHz External Low Speed Crystal LXT 32 768kHz XT1 XT2 Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are four methods of generating the...

Page 79: ...xternal capacitors However for some crystal types and frequencies to ensure oscillation it may be necessary to add two small value capacitors C1 and C2 Using a ceramic resonator will usually require two small value capacitors C1 and C2 to be connected as shown for oscillation to occur The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer s specificat...

Page 80: ...stal are necessary to provide oscillation For applications where precise frequencies are essential these components may be required to provide frequency compensation due to different crystal manufacturing tolerances After the LXT oscillator is enabled by setting the LXTEN bit to 1 there is a time delay associated with the LXT oscillator waiting for it to start up When the microcontroller enters th...

Page 81: ...e LXT operating mode switching must be properly controlled before the LXT oscillator clock is selected as the system clock source Once the LXT oscillator clock is selected as the system clock source using the CKS bit field and FSS bit in the SCC register the LXT oscillator operating mode can not be changed It should be note that no matter what condition the LXTSP is set to the LXT oscillator will ...

Page 82: ... main system clock can come from either a high frequency fH or low frequency fSUB source and is selected using the CKS2 CKS0 bits in the SCC register The high speed system clock is sourced from an HXT or HIRC oscillator selected via configuring the FHS bit in the SCC register The low speed system clock source can be sourced from the internal clock fSUB If fSUB is selected then it can be sourced by...

Page 83: ...LIRC clock will be switched on since the WDT function is always enabled NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the hi...

Page 84: ...it in the SCC register is low In the IDLE2 Mode the CPU will be switched off but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational Control Registers The registers SCC HIRCC HXTC and LXTC are used to control the system clock and the corresponding oscillator configurations Register Name Bit 7 6 5 4 3 2 1 0 SCC CKS2 CKS1 CKS0 FHS FSS F...

Page 85: ...or clock source or the WDT function is enabled respectively If this bit is cleared to 0 but the WDT function is enabled the LIRC oscillator will also be enabled HIRCC Register Bit 7 6 5 4 3 2 1 0 Name HIRC1 HIRC0 HIRCF HIRCEN R W R W R W R W R W POR 0 0 0 1 Bit 7 4 Unimplemented read as 0 Bit 3 2 HIRC1 HIRC0 HIRC frequency selection 00 8 MHz 01 12 MHz 10 16 MHz 11 8 MHz When the HIRC oscillator is...

Page 86: ...ble control 0 Disable 1 Enable LXTC Register Bit 7 6 5 4 3 2 1 0 Name LXTSP LXTF LXTEN R W RW R R W POR 0 0 0 Bit 7 3 Unimplemented read as 0 Bit 2 LXTSP LXT oscillator speed up control 0 Disable Low power 1 Enable Speed up This bit is used to control whether the LXT oscillator is operating in the low power or quick start mode When the LXTSP bit is set to 1 the LXT oscillator will oscillate quickl...

Page 87: ... SLOW Mode is executed using the CKS2 CKS0 bits in the SCC register while Mode Switching from the NORMAL SLOW Modes to the SLEEP IDLE Modes is executed via the HALT instruction When an HALT instruction is executed whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the FHIDEN and FSIDEN bits in the SCC register NORMAL fSYS fH fH 64 fH on CPU run fSYS on fSUB...

Page 88: ...h will consume less power Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs NORMAL Mode SLOW Mode CKS2 CKS0 111 SLEEP Mode FHI...

Page 89: ...EN 0 HALT instruction is executed IDLE0 Mode FHIDEN 0 FSIDEN 1 HALT instruction is executed IDLE1 Mode FHIDEN 1 FSIDEN 1 HALT instruction is executed IDLE2 Mode FHIDEN 1 FSIDEN 0 HALT instruction is executed Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the HALT instruction in the application program with both the FHIDEN and FSIDEN bits...

Page 90: ...egister equal to 1 When this instruction is executed under the conditions described above the following will occur The fH and fSUB clocks will be on but the application program will stop at the HALT instruction The Data Memory contents and registers will maintain their present condition The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set ...

Page 91: ...ed off However when the device is woken up again it will take a considerable time for the original system oscillator to restart stablise and allow normal operation to resume After the system enters the SLEEP or IDLE Mode it can be woken up from one of various sources listed as follows An external falling edge on Port A A system interrupt A WDT overflow When the device executes the HALT instruction...

Page 92: ...e WDTC register Watchdog Timer Control Register A single register WDTC controls the required timeout period as well as the enable disable operation This register controls the overall operation of the Watchdog Timer WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function enable control 10101 or 01010...

Page 93: ...re are five bits WE4 WE0 in the WDTC register to offer the enable disable control and reset control of the Watchdog Timer The WDT function will be enabled when the WE4 WE0 bits are set to a value of 01010B or 10101B If the WE4 WE0 bits are set to any other values other than 01010B and 10101B it will reset the device after 2 3 fLIRC clock cycles After power on these bits will have a value of 01010B...

Page 94: ...ro forcing the microcontroller to begin program execution from the lowest Program Memory address In addition to the power on reset another reset exists in the form of a Low Voltage Reset LVR where a full reset is implemented in situations where the power supply voltage falls below a certain threshold Another type of reset is when the Watchdog Timer overflows and resets the microcontroller All type...

Page 95: ...R W R W R W POR 0 1 0 1 0 1 0 1 Bit 7 0 RSTC7 RSTC0 Reset function control 01010101 No operation 10101010 No operation Other values Reset MCU If these bits are changed due to adverse environmental conditions the microcontroller will be reset The reset operation will be activated after 2 3 LIRC clock cycles and the RSTF bit in the RSTFC register will be set to 1 RSTFC Register Bit 7 6 5 4 3 2 1 0 N...

Page 96: ...se the LVR will reset the device after 2 3 fLIRC clock cycles When this happens the LRF bit in the RSTFC register will be set to 1 After power on the register will have the value of 01010101B Note that the LVR function will be automatically disabled when the device enters the power down mode LVR Inte nal Reset tRSTD tSST Note tRSTD is power on delay with typical time 50 ms Low Voltage Reset Timing...

Page 97: ...nction Note that this bit can only be cleared to 0 by the application program Bit 0 WRF WDT control register software reset flag Described elsewhere Watchdog Time out Reset during Normal Operation The Watchdog time out Reset during normal operation is the same as the hardware Low Voltage Reset except that the Watchdog time out flag TO will be set to 1 WDT Ti e out Inte nal Reset tRSTD tSST Note tR...

Page 98: ...u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power on reset occurs Item Reset Function Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Time Base Clear after reset WDT begins counting Timer Modules Timer Modules will be turned off Input Output Ports I O ports will be setup as inp...

Page 99: ... 0 0 0 0 0 0 0 u u u u u u u u MP2H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u RSTFC 0 x 0 0 u 1 u u u u u u u u u u INTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u INTC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PA 1111 1111 1111 1111 1111 1111 u u u u u u u u PAC 1111 11...

Page 100: ...u u u u u u u SIMC0 111 0 0 0 0 111 0 0 0 0 111 0 0 0 0 u u u u u u u SIMC1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 u u u u u u u u SIMD x x x x x x x x x x x x x x x x x x x x x x x x u u u u u u u u SIMA SIMC2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 101: ...0 0 0 0 0 0 0 u u u u u u u u STMAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u STMAH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u STMRP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM1C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u CTM1DL 0 0 0 0 0 0...

Page 102: ... 1 0 0 111 0 0 1 0 0 u u u u u u u u TKM216DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM216DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM2ROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM2ROH 0 0 0 0 0 0 u u TKM2C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u TKM2C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u TKM...

Page 103: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PBS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PBS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PCS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PCS1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PDS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u ...

Page 104: ...AC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC3 PC2 PC1 PC0 PCC PCC3 PCC2 PCC1 PCC0 PCPU PCPU3 PCPU2 PCPU1 PCPU0 PD PD6 PD5 PD4 PDC PDC6 PDC5 PDC4 PDPU PDPU6 PDPU5 PDPU4 PE PE7 PE6 PE5...

Page 105: ...BC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD6 PD5 PD4 PD3 PD2 PD1 PD0 PDC PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 ...

Page 106: ...DPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PF PF3 PF2 PF1 PF0 PFC PFC3 PFC2 PFC1 PFC0 PFPU PFPU3 PFPU2 PFPU1 PFPU0 PG PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PGC PGC7 PGC6 PGC5 PGC4 PGC3 PGC2 PGC1 PGC0 PGPU PGPU7 PGPU6 PGPU5 PGPU4 PGPU3 PGPU2 PGPU1 PGPU0 PH PH7 PH6 PH5 PH4 PH3 ...

Page 107: ...on one of the Port A pins from high to low This function is especially suitable for applications that can be woken up via external switches Each pin on Port A can be selected individually to have this wake up feature using the PAWU register Note that the wake up function can be controlled by the wake up control registers only when the pin shared functional pin is selected as general purpose input ...

Page 108: ...nding output pin shared function should be configured as the SDI SDA function by configuring the PxSn register and the SDA signal intput should be properly selected using the IFS register However if the external interrupt function is selected to be used the relevant output pin shared function should be selected as an I O function and the interrupt input signal should be selected The most important...

Page 109: ...PCS14 PCS13 PCS12 PCS11 PCS10 PDS0 PDS07 PDS06 PDS05 PDS04 PDS03 PDS02 PDS01 PDS00 PDS1 PDS15 PDS14 PDS13 PDS12 PDS11 PDS10 PES0 PES07 PES06 PES05 PES04 PES03 PES02 PES01 PES00 PES1 PES17 PES16 PES15 PES14 PES13 PES12 PES11 PES10 PFS0 PFS07 PFS06 PFS05 PFS04 PFS03 PFS02 PFS01 PFS00 IFS IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 Pin shared Function Selection Registers List BS67F360 Register Name Bit 7 6 5 4 3 2...

Page 110: ...on 00 10 PA1 01 CTP0 11 V2 Bit 1 0 PAS01 PAS00 PA0 pin function selection 00 10 11 PA0 01 SDO PAS1 Register Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PAS17 PAS16 PA7 pin function selection PAS1 7 6 BS67F340 BS67F350 BS67F360 BS67F370 00 PA7 PA7 PA7 PA7 01 PA7 PA7 PA7 PA7 10 KEY12 KEY20 KEY20 KEY20 11 SEG...

Page 111: ...Bit 3 2 PBS03 PBS02 PB1 pin function selection 00 10 PB1 01 SCK SCL 11 AN1 Bit 1 0 PBS01 PBS00 PB0 pin function selection 00 PB0 01 SDI SDA 10 VREF 11 AN0 PBS1 Register Bit 7 6 5 4 3 2 1 0 Name PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PBS17 PBS16 PB7 pin function selection 00 01 PB7 INT1 10 KEY4 11 AN7 Bit 5 4 PBS15 PBS14 PB6 p...

Page 112: ...PC3 PC3 10 KEY8 KEY8 KEY8 KEY8 11 SEG3 PC3 SEG3 SEG3 Bit 5 4 PCS05 PCS04 PC2 pin function selection PCS0 5 4 BS67F340 BS67F350 BS67F360 BS67F370 00 PC2 PC2 PC2 PC2 01 PC2 PC2 PC2 PC2 10 KEY7 KEY7 KEY7 KEY7 11 SEG2 PC2 SEG2 SEG2 Bit 3 2 PCS03 PCS02 PC1 pin function selection PCS0 3 2 BS67F340 BS67F350 BS67F360 BS67F370 00 PC1 PC1 PC1 PC1 01 PC1 PC1 PC1 PC1 10 KEY6 KEY6 KEY6 KEY6 11 SEG1 PC1 SEG1 SE...

Page 113: ...0 00 PC7 PC7 PC7 01 PC7 PC7 PC7 10 KEY12 KEY12 KEY12 11 PC7 SEG7 SEG7 Bit 5 4 PCS15 PCS14 PC6 pin function selection PCS1 5 4 BS67F340 BS67F350 BS67F360 BS67F370 00 PC6 PC6 PC6 01 PC6 PC6 PC6 10 KEY11 KEY11 KEY11 11 PC6 SEG6 SEG6 Bit 3 2 PCS13 PCS12 PC5 pin function selection PCS1 3 2 BS67F340 BS67F350 BS67F360 BS67F370 00 PC5 PC5 PC5 01 PC5 PC5 PC5 10 KEY10 KEY10 KEY10 11 PC5 SEG5 SEG5 Bit 1 0 PC...

Page 114: ...D3 PD3 PD3 01 PD3 PD3 PD3 10 KEY16 KEY16 KEY16 11 SEG3 SEG11 SEG11 Bit 5 4 PDS05 PDS04 PD2 pin function selection PDS0 5 4 BS67F340 BS67F350 BS67F360 BS67F370 00 PD2 PD2 PD2 01 PD2 PD2 PD2 10 KEY15 KEY15 KEY15 11 SEG2 SEG10 SEG10 Bit 3 2 PDS03 PDS02 PD1 pin function selection PDS0 3 2 BS67F340 BS67F350 BS67F360 BS67F370 00 PD1 PD1 PD1 01 PD1 PD1 PD1 10 KEY14 KEY14 KEY14 11 SEG1 SEG9 SEG9 Bit 1 0 P...

Page 115: ...ection PDS1 5 4 BS67F340 BS67F350 BS67F360 BS67F370 00 PD6 PD6 PD6 PD6 01 PD6 PD6 PD6 PD6 10 KEY11 KEY19 KEY19 KEY19 11 SEG6 SEG6 SEG14 SEG14 Bit 3 2 PDS13 PDS12 PD5 pin function selection PDS1 3 2 BS67F340 BS67F350 BS67F360 BS67F370 00 PD5 PD5 PD5 PD5 01 PD5 PD5 PD5 PD5 10 KEY10 KEY18 KEY18 KEY18 11 SEG5 SEG5 SEG13 SEG13 Bit 1 0 PDS11 PDS10 PD4 pin function selection PDS1 1 0 BS67F340 BS67F350 BS...

Page 116: ... STPI PE3 STPI KEY24 KEY24 11 SEG15 SEG11 SEG19 SEG19 Bit 5 4 PES05 PES04 PE2 pin function selection PES0 5 4 BS67F340 BS67F350 BS67F360 BS67F370 00 PE2 STPI PE2 STPI PE2 STPI PE2 STPI 01 STP STP STP STP 10 OSC2 OSC2 KEY23 KEY23 11 SEG14 SEG10 SEG18 SEG18 Bit 3 2 PES03 PES02 PE1 pin function selection PES0 3 2 BS67F340 BS67F350 BS67F360 BS67F370 00 PE1 PE1 PE1 PE1 01 PE1 PE1 PE1 PE1 10 OSC1 OSC1 K...

Page 117: ...G11 SEG15 SEG23 SEG23 Bit 5 4 PES15 PES14 PE6 pin function selection PES1 5 4 BS67F340 BS67F350 BS67F360 BS67F370 00 PE6 PE6 PE6 PE6 01 CTP1 CTP1 CTP1 CTP1 10 KEY15 PE6 KEY27 KEY27 11 SEG10 SEG14 SEG22 SEG22 Bit 3 2 PES13 PES12 PE5 pin function selection PES1 3 2 BS67F340 BS67F350 BS67F360 BS67F370 00 PE5 CTCK1 PE5 CTCK1 PE5 CTCK1 PE5 CTCK1 01 PE5 CTCK1 PE5 CTCK1 PE5 CTCK1 PE5 CTCK1 10 KEY14 PE5 C...

Page 118: ...t 3 2 PFS03 PFS02 PF1 pin function selection 00 01 PF1 10 OSC2 11 SEG29 Bit 1 0 PFS01 PFS00 PF0 pin function selection 00 01 PF0 10 OSC1 11 SEG28 PGS0 Register BS67F370 Bit 7 6 5 4 3 2 1 0 Name PGS07 PGS06 PGS05 PGS04 PGS03 PGS02 PGS01 PGS00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PGS07 PGS06 PG3 pin function selection 00 PG3 01 PG3 10 KEY32 11 SEG27 Bit 5 4 PGS05 PGS04 PG2...

Page 119: ...01 11 PG6 10 KEY35 Bit 3 2 PGS13 PGS12 PG5 pin function selection 00 01 11 PG5 10 KEY34 Bit 1 0 PGS11 PGS10 PG4 pin function selection 00 01 11 PG4 10 KEY33 PHS0 Register BS67F370 Bit 7 6 5 4 3 2 1 0 Name PHS07 PHS06 PHS05 PHS04 PHS03 PHS02 PHS01 PHS00 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PHS07 PHS06 PH3 pin function selection 00 01 10 PH3 11 SEG43 Bit 5 4 PHS05 PHS04 PH...

Page 120: ... PHS14 PH6 pin function selection 00 01 10 PH6 11 SEG46 Bit 3 2 PHS13 PHS12 PH5 pin function selection 00 01 10 PH5 11 SEG45 Bit 1 0 PHS11 PHS10 PH4 pin function selection 00 01 10 PH4 11 SEG44 IFS Register Bit 7 6 5 4 3 2 1 0 Name IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 4 IFS5 IFS4 SCS input source pin selection 00 10 PA2 01 ...

Page 121: ...e the internal structures of some generic I O pin types As the exact logical construction of the I O pin will differ from these drawings they are supplied as a guide only to assist with the functional understanding of the I O pins The wide range of pin shared structures does not permit all types to be shown Generic Input Output Structure A D Input Output Structure ...

Page 122: ...s on Port A can be setup to have this function Timer Modules TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time To implement time related functions the device includes several Timer Modules generally abbreviated to the name TM The TMs are multi purpose timing units and serve to provide operations such as Timer Counter Input Capture Co...

Page 123: ...comparator P which generate a TM interrupt when a compare match condition occurs When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin TM External Pins Each of the TMs irrespective of what type has one or two TM input pins with the label xTCKn and xTPnI respectively The xTMn input pin xTCKn is essentially a clock source for the xTMn ...

Page 124: ...sing the relevant pin shared function selection registers with the corresponding selection bits in each pin shared function register corresponding to a TM input output pin Configuring the selection bits correctly will setup the corresponding pin as a TM input output The details of the pin shared function selection are described in the pin shared function section CTMn CTCKn CTPn CCR output CTPnB CT...

Page 125: ...ow byte registers named xTMnAL and PTMRPL using the following access procedures Accessing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values Data Bus 8 it Buffe xTMnDH xTMnDL xTMnAH xTMnAL xTMn Counte Registe Read only xTMn CCRA Register Read Write PTMRPH PTMRPL PTM CCRP Register Read Write The following steps show the read and write p...

Page 126: ... Type TM Block Diagram n 0 or 1 Compact TM Operation The Compact TM core is a 10 bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP is three bit wide whose value is compared with t...

Page 127: ...nCK0 CTnON CTnRP2 CTnRP1 CTnRP0 CTMnC1 CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR CTMnDL D7 D6 D5 D4 D3 D2 D1 D0 CTMnDH D9 D8 CTMnAL D7 D6 D5 D4 D3 D2 D1 D0 CTMnAH D9 D8 10 bit Compact TM Registers List n 0 or 1 CTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 CTMn Counter Low Byte Register bit 7 bit 0 CTMn 10 bit Counter b...

Page 128: ...0 fH 16 011 fH 64 100 fSUB 101 fSUB 110 CTCKn rising edge clock 111 CTCKn falling edge clock These three bits are used to select the clock source for the CTMn The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the oscillator section Bit 3 CT...

Page 129: ...all three bits to zero is in effect allowing the counter to overflow at its maximum value CTMnC1 Register Bit 7 6 5 4 3 2 1 0 Name CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 CTnM1 CTnM0 Select CTMn Operating Mode 00 Compare Match Output Mode 01 Undefined 10 PWM Mode 11 Timer Counter Mode These bits setup the required operat...

Page 130: ...high PWM Output Mode 0 Active low 1 Active high This is the output control bit for the CTMn output pin Its operation depends upon whether CTMn is being used in the Compare Match Output Mode or in the PWM Mode It has no effect if the CTMn is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the CTMn output pin before a compare match occurs In the PWM Mode i...

Page 131: ...parator A However here only the CTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when CTnCCLR is high no CTMnPF interrupt request flag will be generated If the CCRA bits are all zero the counter will overflow when its reaches its maximum 10 bit 3FF Hex value however here the CTMnAF interrupt request flag will not b...

Page 132: ...tial Level Low if CTnOC 0 Output Toggle with CTMnAF flag Note CTnIO 1 0 10 Active High Output select Here CTnIO 1 0 11 Toggle Output sele t Output not affe ted y CTMnAF flag Remains High until reset by CTnON bit Output Pin Reset to Initial value Output ont olled y othe pin sha ed fun tion Output Inve ts when CTnPOL is high Compare Match Output Mode CTnCCLR 0 Note 1 With CTnCCLR 0 a Comparator P ma...

Page 133: ...O 1 0 11 Toggle Output sele t Output not affe ted y CTMnAF flag Remains High until reset by CTnON bit Output Pin Reset to Initial value Output ont olled y othe pin sha ed fun tion Output Inve ts when CTnPOL is high CTMnPF not gene ated No CTMnAF flag gene ated on CCRA ove flow Output does not hange CCRA Int flag CTMnAF CCRP Int flag CTMnPF Compare Match Output Mode CTnCCLR 1 Note 1 With CTnCCLR 1 ...

Page 134: ...te the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTnDPX bit in the CTMnC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP reg...

Page 135: ...rns high CTnDPX 0 CTnM 1 0 10 PWM Duty Cy le set y CCRA PWM esu es ope ation Output ont olled y othe pin sha ed fun tion Output Inve ts when CTnPOL 1 PWM Pe iod set y CCRP CTMn O P Pin CTnOC 0 CCRA Int flag CTMnAF CCRP Int flag CTMnPF PWM Output Mode CTnDPX 0 Note 1 Here CTnDPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues even when CTnIO1 CTnIO0...

Page 136: ...f CTnON bit low Counte Reset when CTnON returns high CTnDPX 1 CTnM 1 0 10 PWM Duty Cy le set y CCRP PWM esu es ope ation Output ont olled y othe pin sha ed fun tion Output Inve ts when CTnPOL 1 PWM Pe iod set y CCRA CTMn O P Pin CTnOC 0 PWM Output Mode CTnDPX 1 Note 1 Here CTnDPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even when CTnIO 1 0 0...

Page 137: ... TM Operation The size of Standard TM is 16 bit wide and its core is a 16 bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP comparator is 8 bit wide whose value is compared the wi...

Page 138: ...8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH D15 D14 D13 D12 D11 D10 D9 D8 STMRP STRP7 STRP6 STRP5 STRP4 STRP3 STRP2 STRP1 STRP0 16 bit Standard TM Registers List STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 STM Counter Low Byte Register bit 7 bit 0 STM 16 bit Counter bit 7 bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11...

Page 139: ...ct the clock source for the STM The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the oscillator section Bit 3 STON STM Counter On Off control 0 Off 1 On This bit controls the overall on off function of the STM Setting the bit high enables ...

Page 140: ...e how the STM output pin changes state when a certain condition is reached The function that these bits select depends upon in which mode the STM is running In the Compare Match Output Mode the STIO1 and STIO0 bits determine how the STM output pin changes state when a compare match occurs from the Comparator A The TM output pin can be setup to switch high switch low or to toggle its present state ...

Page 141: ...s set high the STM output pin will be inverted and not inverted when the bit is zero It has no effect if the STM is in the Timer Counter Mode Bit 1 STDPX STM PWM duty period control 0 CCRP period CCRA duty 1 CCRP duty CCRA period This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform Bit 0 STCCLR STM Counter Clear condition selection 0 Com...

Page 142: ...er overflow a compare match from Comparator A and a compare match from Comparator P When the STCCLR bit is low there are two ways in which the counter can be cleared One is when a compare match from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively will both...

Page 143: ...initial Level Low if STOC 0 Output Toggle with STMAF flag Note STIO 1 0 10 Active High Output select Here STIO 1 0 11 Toggle Output sele t Output not affe ted y STMAF flag Remains High until reset by STON bit Output Pin Reset to Initial value Output ont olled y othe pin sha ed fun tion Output Inve ts when STPOL is high Compare Match Output Mode STCCLR 0 Note 1 With STCCLR 0 a Comparator P match wi...

Page 144: ...TIO 1 0 10 Active High Output select Here STIO 1 0 11 Toggle Output sele t Output not affe ted y STMAF flag Remains High until reset by STON bit Output Pin Reset to Initial value Output ont olled y othe pin sha ed fun tion Output Inve ts when STPOL is high STMPF not gene ated No STMAF flag gene ated on CCRA ove flow Output does not hange Compare Match Output Mode STCCLR 1 Note 1 With STCCLR 1 a Co...

Page 145: ...period Both of the CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register The PWM waveform frequency and duty cycle can the...

Page 146: ... if STON bit low Counte Reset when STON returns high STDPX 0 STM 1 0 10 PWM Duty Cy le set y CCRA PWM esu es ope ation Output ont olled y othe pin sha ed fun tion Output Inve ts when STPOL 1 PWM Pe iod set y CCRP STM O P Pin STOC 0 PWM Output Mode STDPX 0 Note 1 Here STDPX 0 Counter cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when STIO 1...

Page 147: ...Stop if STON bit low Counte Reset when STON returns high STDPX 1 STM 1 0 10 PWM Duty Cy le set y CCRP PWM esu es ope ation Output ont olled y othe pin sha ed fun tion Output Inve ts when STPOL 1 PWM Pe iod set y CCRA STM O P Pin STOC 0 PWM Output Mode STDPX 1 Note 1 Here STDPX 1 Counter cleared by CCRA 2 A counter clear sets the PWM Period 3 The internal PWM function continues even when STIO 1 0 0...

Page 148: ...ng and the pulse leading edge will be generated The STON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the STON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the STON bit and ...

Page 149: ... 0 11 Pulse Width set y CCRA Output Inve ts when STPOL 1 No CCRP Interrupts gene ated STM O P Pin STOC 0 STCK pin Softwa e T igge Clea ed y CCRA at h STCK pin T igge Auto set y STCK pin Softwa e T igge Softwa e Clea Softwa e T igge Softwa e T igge Single Pulse Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the STCK pin or by setting the STON bit high 4 A STCK pin a...

Page 150: ...ears on the STPI pin the present value in the counter will be latched into the CCRA registers and a STM interrupt generated Irrespective of what events occur on the STPI pin the counter will continue to free run until the STON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value...

Page 151: ...I XX Counte Stop STIO 1 0 Value XX YY XX YY A tive edge A tive edge A tive edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disa le Captu e Capture Input Mode Note 1 STM 1 0 01 and active edge set by the STIO 1 0 bits 2 A STM Capture input pin active edge transfers the counter value to CCRA 3 STCCLR bit not used 4 No output function STOC and STPOL bits are not used 5 CCRP determines the counte...

Page 152: ...PTS PTPB Periodic Type TM Block Diagram Periodic TM Operation The size of Periodic TM is 10 bit wide and its core is a 10 bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP and CCR...

Page 153: ...M0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR PTMDL D7 D6 D5 D4 D3 D2 D1 D0 PTMDH D9 D8 PTMAL D7 D6 D5 D4 D3 D2 D1 D0 PTMAH D9 D8 PTMRPL PTRP7 PTRP6 PTRP5 PTRP4 PTnRP3 PTRP2 PTRP1 PTRP0 PTMRPH PTRP9 PTRP8 Periodic TM Registers List PTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 0 PTM Counter Low Byte Register bit 7 bit 0 PTM 10 bit Counter ...

Page 154: ...it 0 PTMRPH Register Bit 7 6 5 4 3 2 1 0 Name PTRP9 PTRP8 R W R W R W POR 0 0 Bit 7 2 Unimplemented read as 0 Bit 1 0 PTRP9 PTRP8 PTM CCRP High Byte Register bit 1 bit 0 PTM 10 bit CCRP bit 9 bit 8 PTMC0 Register Bit 7 6 5 4 3 2 1 0 Name PTPAU PTCK2 PTCK1 PTCK0 PTON R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 PTPAU PTM Counter Pause control 0 Run 1 Pause The counter can be paused by setting this b...

Page 155: ...o however when the bit changes from high to low the internal counter will retain its residual value until the bit returns high again If the PTM is in the Compare Match Output Mode then the PTM output pin will be reset to its initial condition as specified by the PTOC bit when the PTON bit changes from low to high Bit 2 0 Unimplemented read as 0 PTMC1 Register Bit 7 6 5 4 3 2 1 0 Name PTM1 PTM0 PTI...

Page 156: ...to its initial level by changing the level of the PTON bit from low to high In the PWM Mode the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs The PTM output function is modified by changing these two bits It is necessary to only change the values of the PTIO1 and PTIO0 bits only after the PTM has been switched off Unpredictable PWM...

Page 157: ...the PTCCLR bit is low there are two ways in which the counter can be cleared One is when a compare match from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both PTMAF and PTMPF interrupt request flags for Comparator A and Comparator P respectively will both be generated If the PTCCLR bit in the PTMC1 register is high then the counter will be cl...

Page 158: ...initial Level Low if PTOC 0 Output Toggle with PTMAF flag Note PTIO 1 0 10 Active High Output select Here PTIO 1 0 11 Toggle Output sele t Output not affe ted y PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output ont olled y othe pin sha ed fun tion Output Inve ts when PTPOL is high Compare Match Output Mode PTCCLR 0 Note 1 With PTCCLR 0 a Comparator P match wi...

Page 159: ...IO 1 0 10 Active High Output select Here PTIO 1 0 11 Toggle Output sele t Output not affe ted y PTMAF flag Remains High until reset by PTON bit Output Pin Reset to Initial value Output ont olled y othe pin sha ed fun tion Output Inve ts when PTPOL is high PTMPF not gene ated No PTMAF flag gene ated on CCRA ove flow Output does not hange Compare Match Output Mode PTCCLR 1 Note 1 With PTCCLR 1 a Com...

Page 160: ... varying equivalent DC RMS values As both the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM mode the PTCCLR bit has no effect as the PWM period Both of the CCRP and CCRA registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while t...

Page 161: ... e Counte Stop if PTON bit low Counte Reset when PTON returns high PTM 1 0 10 PWM Duty Cy le set y CCRA PWM esu es ope ation Output ont olled y othe pin sha ed fun tion Output Inve ts When PTPOL 1 PWM Pe iod set y CCRP PTM O P Pin PTOC 0 PWM Mode Note 1 The counter is cleared by CCRP 2 A counter clear sets the PWM Period 3 The internal PWM function continues running even when PTIO 1 0 00 or 01 4 T...

Page 162: ...rt running and the pulse leading edge will be generated The PTON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PTON bit is cleared to zero which can be implemented using the application program or when a compare match occurs from Comparator A However a compare match from Comparator A will also automatically clear the PTON ...

Page 163: ... 0 11 Pulse Width set y CCRA Output Inve ts when PTPOL 1 No CCRP Interrupts gene ated PTM O P Pin PTOC 0 PTCK pin Softwa e T igge Clea ed y CCRA at h PTCK pin T igge Auto set y PTCK pin Softwa e T igge Softwa e Clea Softwa e T igge Softwa e T igge Single Pulse Mode Note 1 Counter stopped by CCRA 2 CCRP is not used 3 The pulse triggered by the PTCK pin or by setting the PTON bit high 4 A PTCK pin a...

Page 164: ...PTM interrupt generated Irrespective of what events occur on the PTPI or PTCK pin the counter will continue to free run until the PTON bit changes from high to low When a CCRP compare match occurs the counter will reset back to zero in this way the CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a PTM interrupt will also be generated C...

Page 165: ... PTCK XX Counte Stop PTIO 1 0 Value XX YY XX YY A tive edge A tive edge A tive edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disa le Captu e Capture Input Mode Note 1 PTM 1 0 01 and active edge set by the PTIO 1 0 bits 2 A PTM Capture input pin active edge transfers the counter value to CCRA 3 PTCCLR bit not used 4 No output function PTOC and PTPOL bits are not used 5 CCRP determines the co...

Page 166: ...ature semsor output or Temperature sensor reference voltage into a 12 bit digital value The external or internal analog signal to be converted is determined by the ACS3 ACS0 bits together with the TSE and BGMEN bits When the external analog signal is to be converted the corresponding pin shared control bits should first be properly configured and then desired external channel input should be selec...

Page 167: ...ontrolled using eight registers A read only register pair exists to store the A D Converter data 12 bit value Two registers ADCR0 and ADCR1 are the control registers which setup the operating and control function of the A D converter The remaining four registers are the temperature sensor control registers which select the temperature sensor signal to be converted and the reference voltage source ...

Page 168: ...nd ADCR1 are provided These 8 bit registers define functions such as the selection of which analog channel is connected to the internal A D converter the digitised data format the A D clock source as well as controlling the start function and monitoring the A D converter busy status As these devices contain only one actual analog to digital converter hardware circuit each of the external and inter...

Page 169: ...the A D converter If the bit is set low then the A D converter will be switched off reducing the device power consumption When the A D converter function is disabled the contents of the A D data register pair known as ADRH and ADRL will be cleared to zero Bit 4 ADRFS A D conversion data format select 0 A D converter data format ADRH D 11 4 ADRL D 3 0 1 A D converter data format ADRH D 11 8 ADRL D ...

Page 170: ...PU idle mode will be enabled The CPU will not operate when the A D converter is operating with the IDLE_CONV bit being set to 1 until the conversion is completed Bit 4 VREFS A D converter reference voltage select 0 Internal A D converter power 1 VREF pin This bit is used to select the A D converter reference voltage and only available when the VREFP_EXT bit in the TSC2 register is set to 1 It is r...

Page 171: ...ain select 0 Gain 4 1 Gain 5 This bit controls the OPA2 gain selection This bit should be properly selected for different temperature range applications to avoid the saturated code Bit 5 K_REFO OPA1 gain select 0 Gain 1 675 1 Gain 1 This bit is used to select the OPA1 gain to determine the temperature sensor reference voltage output value Bit 4 0 Unimplemented read as 0 TSC1 Register Bit 7 6 5 4 3...

Page 172: ...r configurations of the OPA2 input signal and gain Bit 6 BIAS OPA2 bias voltage select 0 VTSVREF 1 Internal A D converter power Bit 5 2 D5 D2 Data bits for internal used These bits should be kept low and can not be changed Bit 1 0 TSCLK_S1 TSCLK_S0 Temperature sensor clock source tTSCLK select 00 tTSCLK tADCK 4 01 tTSCLK tADCK 8 1x tTSCLK tADCK 16 The temperature sensor signal conversion time can ...

Page 173: ...o 10μs care must be taken for system clock frequencies For example as the system clock operates at a frequency of 8MHz the ADCK2 ADCK0 bits should not be set to 000 001 or 111 Doing so will give A D clock periods that are less than the minimum A D clock period which may result in inaccurate A D conversion values Refer to the following table for examples where values marked with an asterisk show wh...

Page 174: ...f the pins are setup as A D inputs Note that it is not necessary to first setup the A D pin as an input in the port control register to enable the A D input as when the relevant A D input function selection bits enable an A D input the status of the port control register will be overridden The A D converter has its own reference voltage pin VREF However the reference voltage can also be supplied f...

Page 175: ...is selected If the TSE bit is 1 and ACS3 ACS0 bits are equal to 1xxx then the relevant internal temperature sensor signal is selected Step 4 Select the reference voltgage source by configuring the K_VPTAT K_REFO and VREFS bits Step 5 Select the A D converter output data format by configuring the ADRFS bit Step 6 If A D conversion interrupt is used the interrupt control registers must be correctly ...

Page 176: ...power consumption A D Transfer Function As the devices contain a 12 bit A D converter its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to the reference voltage this gives a single bit analog input value of reference voltage value divided by 4096 1 LSB VREF 4096 The A D Converter input voltage value can be calculated using the following equa...

Page 177: ..._EXT deselect the temperature sensor reference voltage mov a 03H select fSYS 8 as A D clock and A D internal power supply mov ADCR1 a as reference voltage set ADCEN mov a 03H setup PBS0 to configure pin AN0 mov PBS0 a mov a 20H mov ADCR0 a enable and connect AN0 channel to A D converter start_conversion clr START high pulse on start bit to initiate conversion set START reset A D clr START start A ...

Page 178: ...onversion clr START high pulse on START bit to initiate conversion set START reset A D clr START start A D clr ADF clear ADC interrupt request flag set ADE enable ADC interrupt set EMI enable global interrupt ADC_ISR ADC interrupt service routine mov acc_stack a save ACC to user defined memory mov a STATUS mov status_stack a save STATUS to user defined memory mov a ADRL read low byte conversion re...

Page 179: ...aster or slave Although the SPI interface specification can control multiple slave devices from a single master these devices provided only one SCS pin If the master needs to control multiple slave devices from a single master the master can use I O pin to select the slave devices SPI Interface Operation The SPI interface is a full duplex synchronous serial data link It is a four line interface wi...

Page 180: ...0 SIMEN SIMICF SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF SIMD D7 D6 D5 D4 D3 D2 D1 D0 SPI Registers List SIMD Register The SIMD register is used to store the data being transmitted and received The same register is used by both the SPI and I2 C functions Before the device writes data to the SPI bus the actual data to be transmitted must be placed in the SIMD register After the data is received fro...

Page 181: ...he overall on off control for the SIM interface When the SIMEN bit is cleared to zero to disable the SIM interface the SDI SDO SCK and SCS or SDA and SCL lines will lose their SPI or I2 C function and the SIM operating current will be reduced to a minimum value When the bit is high the SIM interface is enabled The SIM configuration option must have first enabled the SIM interface for this bit to b...

Page 182: ...dition of the clock line if the bit is high then the SCK line will be low when the clock is inactive When the CKPOLB bit is low then the SCK line will be high when the clock is inactive The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit Bit 3 MLS SPI data shift order 0 LSB first 1 MSB first This is the data shift select bit and is used to select how the d...

Page 183: ...m the master has been received any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register The master should output a SCS signal to enable the slave devices before a clock signal is provided The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the C...

Page 184: ...F340 BS67F350 BS67F360 BS67F370 Enhanced Touch A D Flash MCU with LCD Driver Note For SPI slave mode if SIMEN 1 and CSEN 0 the SPI is always enabled and ignores the SCS level SPI Slave Mode Timing CKEG 1 SPI Transfer Control Flow Chart ...

Page 185: ...terface is a two line interface a serial data line SDA and serial clock line SCL As many devices may be connected together on the same bus their outputs are both open drain types For this reason it is necessary that external pull high resistors are connected to these outputs Note that no chip select line exists as each device on the I2 C bus is identified by a unique address which will be transmit...

Page 186: ... users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table I2 C Debounce Time Selection I2 C Standard Mode 100kHz I2 C Fast Mode 400kHz No Devounce fSYS 2 MHz fSYS 5 MHz 2 system clock debounce fSYS 4 MHz fSYS 10 MHz 4 system clock debounce fSYS 8 MHz fSYS 20 MHz I2 C Minimum fSYS Frequency I2 C Registers There ...

Page 187: ...re the 7 bit slave address of the slave device is stored Bits 7 1 of the SIMA register define the device slave address Bit 0 is not defined When a master device which is connected to the I2 C bus sends out an address which matches the slave address in the SIMA register the slave device will be selected Note that the SIMA register is the same register address as SIMC2 which is used by the SPI inter...

Page 188: ...01 2 system clock debounce 1x 4 system clock debounce Bit 1 SIMEN SIM Enable Control 0 Disable 1 Enable The bit is the overall on off control for the SIM interface When the SIMEN bit is cleared to zero to disable the SIM interface the SDI SDO SCK and SCS or SDA and SCL lines will lose their SPI or I2 C function and the SIM operating current will be reduced to a minimum value When the bit is high t...

Page 189: ...mit acknowledge flag 0 Slave send acknowledge flag 1 Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag After the slave device receipt of 8 bits of data this bit will be transmitted to the bus on the 9th clock from the slave device The slave device must always set TXAK bit to 0 before further data is received Bit 2 SRW I2 C slave read write flag 0 Slave device shoul...

Page 190: ...l of data on the bus The first seven bits of the data will be the slave address with the first bit being the MSB If the address of the slave device matches that of the transmitted address the HAAS bit in the SIMC1 register will be set and an I2 C interrupt will be generated After entering the interrupt service routine the slave device must first check the condition of the HAAS and SIMTOF bits to d...

Page 191: ...te status and will be saved to the SRW bit of the SIMC1 register The slave device will then transmit an acknowledge bit which is a low level as the 9th bit The slave device will also set the status flag HAAS when the addresses match As an I2 C bus interrupt can come from three sources when the program enters the interrupt subroutine the HAAS and SIMTOF bits should be examined to see whether the in...

Page 192: ...eipt of its slave address The order of serial bit transmission is the MSB first and the LSB last After receipt of 8 bits of data the receiver must transmit an acknowledge signal level 0 before it can receive the next data byte If the slave transmitter does not receive an acknowledge bit signal from the master receiver then the slave transmitter will release the SDA line to allow the master to send...

Page 193: ...ce connected to the I2 C bus is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts to count on an I2 C bus START address match condition and is cleared by an SCL falling edge Before the next SCL falling edge arrives if the time elapsed is greater than the time out period specified by the SIMTOC register then a ti...

Page 194: ... be reset and the registers will be reset into the following condition Register After I2 C Time out SIMD SIMA SIMC0 No change SIMC1 Reset to POR condition I2 C Register after Time out The SIMTOF flag can be cleared by the application program There are 64 time out period selections which can be selected using the SIMTOS bits in the SIMTOC register The time out duration is calculated by the formula ...

Page 195: ...en a transmission terminates The integrated UART function contains the following features Full duplex asynchronous communication 8 or 9 bits character length Even odd or no parity options One or two stop bits Baud rate generator with 8 bit prescaler Parity framing noise and overrun error detection Support for interrupt on address detect last character bit 1 Separately enabled transmitter and recei...

Page 196: ...U Data Memory the Transmit Shift Register is not mapped and is therefore inaccessible to the application program Data to be received by the UART is accepted on the external RX pin from where it is shifted in LSB first to the Receiver Shift Register at a rate controlled by the Baud Rate Generator When the shift register is full the data will then be transferred from the shift register to the intern...

Page 197: ...hen the flag is 1 it indicates that the UART has detected noise on the receiver input The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register Bit 5 FERR Framing error flag 0 No framing error is detected...

Page 198: ...ister is read with RXIF set followed by a read from the RXR register and if the RXR register has no data available Bit 1 TIDLE Transmission status 0 data transmission is in progress data being transmitted 1 no data transmission is in progress transmitter is idle The TIDLE flag is known as the transmission complete flag When this read only flag is 0 it indicates that a transmission is in progress T...

Page 199: ...sters will remain unaffected If the UART is active and the UARTEN bit is cleared all pending transmissions and receptions will be terminated and the module will be reset as defined above When the UART is re enabled it will restart in the same configuration Bit 6 BNO Number of data transfer bits selection 0 8 bit data transfer 1 9 bit data transfer This bit is used to select the data length format ...

Page 200: ...interrupt sources The register also serves to control the baud rate speed receiver wake up function enable and the address detect function enable Further explanation on each of the bits is given below Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN UART Transmitter enable control 0 UART Transmitter is disabled 1 UA...

Page 201: ...isables the receiver wake up function If this bit is equal to 1 and the device is in IDLE0 or SLEEP mode a falling edge on the RX pin will wake up the device If this bit is equal to 0 and the device is in IDLE or SLEEP mode any edge transitions on the RX pin will not wake up the device Bit 2 RIE Receiver interrupt enable control 0 Receiver related interrupt is disabled 1 Receiver related interrupt...

Page 202: ...BRG register the required baud rate can be setup Note that because the actual baud rate is determined using a discrete value N placed in the BRG register there will be an error associated between the actual and requested value The following example shows how the BRG register value N and the error value can be calculated BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 ...

Page 203: ... to an empty condition at the same time discarding any remaining residual data Disabling the UART will also reset the enable control the error and status flags with bits TXEN RXEN TXBRK RXIF OERR FERR PERR and NF being cleared while bits TIDLE TXIF and RIDLE will be set The remaining control bits in the UCR1 UCR2 and BRG registers will remain unaffected If the UARTEN bit in the UCR1 register is cl...

Page 204: ...loading data into the TXR register after which the TXEN bit can be set When a transmission of data begins the TSR is normally empty in which case a transfer to the TXR register will result in an immediate transfer to the TSR If during a transmission the TXEN bit is cleared the transmission will immediately cease and the transmitter will be reset The TX output pin will be in a floating state Transm...

Page 205: ...ansmitting a break character will not generate a transmit interrupt Note that a break condition length is at least 13 bits long If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters After the application program has cleared the TXBRK bit the transmitter will finish transmitting the last break character and subsequently s...

Page 206: ...generated If during reception a frame error noise error parity error or an overrun error has been detected then the error flags can be set The RXIF bit can be cleared using the following software sequence 1 A USR register access 2 A RXR register read execution Receiving Break Any break character received by the UART will be managed as a framing error The receiver will count and expect a certain nu...

Page 207: ...h byte has been entirely shifted in the data should be read from the RXR register If this is not done the overrun error flag OERR will be consequently indicated In the event of an overrun error occurring the following will happen The OERR flag in the USR register will be set The RXR contents will not be lost The shift register will be overwritten An interrupt will be generated if the RIE bit is se...

Page 208: ...e bits can be used to mask out individual UART interrupt sources The address detect condition which is also a UART interrupt source does not have an associated flag but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register An RX pin wake up which is also a UART interrupt source does not have an associated fla...

Page 209: ...e UART will cease to function If the MCU executes the HALT instruction and switches off the system clock while a transmission is still in progress then the transmission will be paused until the UART clock source derived from the microcontroller is activated In a similar way if the MCU executes the HALT instruction and switches off the system clock while receiving data then the reception of data wi...

Page 210: ...or B LCD Selections Note The pin VMAX must be connected to the maximum voltage to prevent from the pad leakage Powe Supply f o pin V Cha ge Pu p VA V1 3 VIN VB PLCD VIN VC V VIN 0 1uF 0 1uF 0 1uF C1 C V1 V VMAX PLCD VIN VDD o V1 Cha ge Pu p VA V1 VIN VB PLCD 2 3 VIN VC V2 1 3 VIN 0 1uF 0 1uF 0 1uF C1 C V1 V VMAX PLCD Powe Supply f o pin V1 VIN VDD o V1 Cha ge Pu p VA V1 3 2 VIN VB PLCD VIN VC V2 1...

Page 211: ...overlap those of the General Purpose Data Memory it is stored in its own independent Sector 4 area The Data Memory sector to be used is chosen by using the Memory Pointer high byte register which is a special function register in the Data Memory with the name MP1H or MP2H To access the LCD Memory therefore requires first that Sector 4 is selected by writing a value of 04H to the MP1H or MP2H regis...

Page 212: ...CH 1DH 1EH 1FH SEG 0 SEG 1 SEG SEG 3 SEG 31 SEG 30 SEG 9 SEG 8 3 1 0 COM 0 COM 1 COM COM 3 32 SEG x 4 COM BS67F340 LCD Memory Map BS67F350 LCD Memory Map 00H 01H 02H 03H 24H 25H 26H 27H SEG 0 SEG 1 SEG SEG 3 SEG 39 SEG 38 SEG 37 SEG 3 3 1 0 COM 0 COM 1 COM COM 3 40 SEG x 4 COM 00H 01H 02H 03H 2CH 2DH 2EH 2FH SEG 0 SEG 1 SEG SEG 3 SEG 47 SEG 4 SEG 4 SEG 44 3 1 0 COM 0 COM 1 COM COM 3 48 SEG x 4 COM...

Page 213: ...e function will only be effective when the device is in the NOAMRL SLOW or IDLE Mode If the device is in the SLEEP Mode then the display will always be disabled Bits RSEL2 RSEL0 in the LCDC0 register select the internal total bias resistors to supply the LCD panel with the proper bias current A choice to best match the LCD panel used in the application can be selected also to minimise bias current...

Page 214: ...IN is an internal reference voltage with an approximate level of 1 08V Bit 3 1 RSEL2 RSEL0 R type total bias resistors selection 000 1170 kΩ 001 225 kΩ 010 60 kΩ 011 Quick charging mode switching between 60 kΩ and 1170 kΩ 1xx Quick charging mode switching between 60 kΩ and 225 kΩ The device provides the low power quick charging mode for R type LCD display In quick charging mode the LCD will provid...

Page 215: ... operation The devices can have either R type or C type biasing selected via a software control bit named RCT Selecting the C type biasing will enable an internal charge pump circuitry R Type Biasing For R type biasing an external LCD voltage source must be supplied on pin PLCD to generate the internal biasing voltages This could be the microcontroller power supply VDD or some other voltage source...

Page 216: ...ised These bias voltages have different levels depending upon different LCD power supply schemes LCD Power Supply VA voltage VB voltage VC voltage External Power Supply VIN on V1 VIN 2 3 VIN 1 3 VIN VIN on PLCD 3 2 VIN VIN 1 2 VIN VIN on V2 3 VIN 2 VIN VIN Internal Power Supply VDD on VA VDD 2 3 VDD 1 3 VDD VDD on VB 3 2 VDD VDD 1 2 VDD VREFIN on VC 3 VREFIN 2 VREFIN VREFIN C Type Bias Power Suppl...

Page 217: ...ust be greater than the LCD saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off The requirement to limit the DC voltage to zero and to control as many pixels as possible with a minimum number of connections requires that both a time and amplitude signal is generated and applied to the application LCD These time and amplitude varying signals are aut...

Page 218: ...ts are ON COM1 side segments are ON COM2 side segments are ON COM3 side segments are ON COM0 1 side segments are ON COM0 2 side segments are ON COM0 3 side segments are ON All sengments are ON othe o inations a e o itted 1 F a e VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS CO...

Page 219: ...ts are ON COM1 side segments are ON COM2 side segments are ON COM3 side segments are ON COM0 1 side segments are ON COM0 2 side segments are ON COM0 3 side segments are ON All sengments are ON othe o inations a e o itted 1 F a e VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS VA VB VC VSS CO...

Page 220: ... consideration that must be taken into account is what happens when the microcontroller enters the IDLE or SLOW Mode The LCDEN control bit in the LCDC0 register permits the display to be powered off to reduce power consumption If this bit is zero the driving signals to the display will cease producing a blank display pattern but reducing any power consumption associated with the LCD After Power on...

Page 221: ...EY5 KEY8 M2 KEY9 KEY12 M3 KEY13 KEY16 M4 KEY17 KEY20 M5 KEY21 KEY24 M6 KEY25 KEY28 M7 KEY29 KEY32 M8 KEY33 KEY36 BS67F360 28 M0 KEY1 KEY4 M1 KEY5 KEY8 M2 KEY9 KEY12 M3 KEY13 KEY16 M4 KEY17 KEY20 M5 KEY21 KEY24 M6 KEY25 KEY28 BS67F350 20 M0 KEY1 KEY4 M1 KEY5 KEY8 M2 KEY9 KEY12 M3 KEY13 KEY16 M4 KEY17 KEY20 BS67F340 16 M0 KEY1 KEY4 M1 KEY5 KEY8 M2 KEY9 KEY12 M3 KEY13 KEY16 Touch Key Structure ...

Page 222: ...KMnROH TKMnROL f o Data Me o y Se to Filte Module n 16 bit C F Counter Filte fSYS 4 M U X MnTSS TKMnC 8 it Ti e Slot Counte it unit pe iod ounte 8 it Ti e Slot Counte P eload Registe TKTMR Ove flow 1 it Counte TK1 OV M U X TK1 S1 TK1 S0 fSYS 4 fSYS 2 fSYS fSYS 8 16 bit C F Counter Value Se to Tou h Key Data Me o y Refe en e Os Capa ito Value Se to Note The structure contained in the dash line is i...

Page 223: ...e n 16 bit C F counter low byte TKMn16DH Touch key module n 16 bit C F counter high byte TKMnROL Touch key module n reference oscillator capacitor select low byte TKMnROH Touch key module n reference oscillator capacitor select high byte TKMnC0 Touch key module n Control register 0 TKMnC1 Touch key module n Control register 1 TKMnC2 Touch key module n Control register 2 Touch Key Module Registers ...

Page 224: ...uto scan mode Otherwise the contents of the touch key RAM may be modified as this RAM space is configured by the touch key module followed by the MCU access Bit 6 TKRCOV Touch key time slot counter overflow flag 0 No overflow occurs 1 Overflow occurs This bit can be accessed by application programs When this bit is set by touch key time slot counter overflow the corrrespondingn touch key interrupt...

Page 225: ...unction 16 bit counter overflow and must be cleared to 0 by application programs Bit 2 Unimplemented read as 0 Bit 1 TKMOD Touch key scan mode select 0 Auto scan mode 1 Manual scan mode In manual scan mode the reference oscillator capacitor value should be properly configured before the scan operation begins and the touch key module 16 bit C F counter value should be read after the scan operation ...

Page 226: ... 16 bit counter value This 16 bit counter can be used to calibrate the reference or key oscillator frequency When the touch key time slot counter overflows in the manual scan mode this 16 bit counter will be stopped and the counter content will be unchanged However this 16 bit counter content will be cleared to zero at the end of the time slot 0 slot 1 and slot 2 but kept unchanged at the end of t...

Page 227: ... 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 MnDFEN Touch key module n multi frequency control 0 Disable 1 Enable This bit is used to control the touch key oscillator frequency doubling function When this bit is set to 1 the key oscillator frequency will be doubled Bit 4 D4 Data bit for test only The bit is used for test purpose only and must be kept as 0 for normal operations Bit 3 MnSOFC Touch k...

Page 228: ... disable the reference oscillator In manual scan mode the reference oscillator should first be enabled before setting the TKST bit from low to high if the reference oscillator is selected to be used and will be disabled when the TKBUSY bit is changed from high to low Bit 4 MnKOEN Touch key module n Key oscillator enable control 0 Disable 1 Enable This bit is used to enable the touch key module n k...

Page 229: ...t 5 4 MnSK21 MnSK20 Touch key module n time slot 2 key scan select 00 KEY 1 01 KEY 2 10 KEY 3 11 KEY 4 These bits are used to select the desired scan key in time slot 2 and only available in the auto scan mode Bit 3 2 MnSK11 MnSK10 Touch key module n time slot 1 key scan select 00 KEY 1 01 KEY 2 10 KEY 3 11 KEY 4 These bits are used to select the desired scan key in time slot 1 and only available ...

Page 230: ...oscillator touch actions can be sensed by measuring these frequency changes Using an internal programmable divider the reference clock is used to generate a fixed time period By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined TKST MnKOEN MnROEN KEY OSC CLK Refe en e OSC CLK fCFTMCK Ena le fCFTMCK MnDFEN 0 fCFTM...

Page 231: ...bit time slot timer counter will be automatically switched on The key oscillator and reference oscillator in all modules will be automatically stopped and the 16 bit C F counter 16 bit counter 5 bit time slot unit period counter and 8 bit time slot timer counter will be automatically switched off when the time slot counter overflows The clock source for the time slot counter is sourced from the re...

Page 232: ...slot Ti e slot 3 TKBUSY TKRCOV Clea ed y softwa e Ti e slot 1 Ti e slot Ti e slot 3 Ti e slot 1 Ti e slot Ti e slot 3 Ti e slot 1 Ti e slot Ti e slot 3 Tou h Key Data Me o y A ess Set Tou h Key inte upt equest flag Read 2N bytes from Touch Key Data Memory to TKMnROH TKMnROL registers Write 2N bytes from TKMn16DH TKMn16DL registers to Tou h Key Data Me o y N Touch Key Module Number n Module Serial ...

Page 233: ...from the touch key data memory and loaded into the the next TKMnROH TKMnROL registers Then the 16 bit C F counter value of the current scanned key will be written into the corresponding touch key data memory The whole auto scan operation will sequentially be carried out in the above specific way from time slot 0 to time slot 3 After four keys are scanned the TKRCOV bit will be set high and the TKB...

Page 234: ...16DH_K1 TKM216DL_K2 TKM216DH_K2 TKM216DL_K3 TKM216DH_K3 TKM216DL_K4 TKM216DH_K4 TKM2ROL_K1 TKM2ROH_K1 TKM2ROL_K2 TKM2ROH_K2 TKM2ROL_K4 TKM2ROH_K4 TKM2ROL_K3 TKM2ROH_K3 Module 1 Module 2 16 bit C F counter value Sector 5 Ref OSC Capacitor value Sector 6 Module n TKMnROL_K1 TKMnROH_K1 TKMnROL_K2 TKMnROH_K2 TKMnROL_K4 TKMnROH_K4 TKMnROL_K3 TKMnROH_K3 TKMn16DL_K1 TKMn16DH_K1 TKMn16DL_K2 TKMn16DH_K2 TK...

Page 235: ...pe ation Sta t Set Sta t it TKST 0 1 Busy flag TKBUSY 1 All Ti e Slot Counte ove flow TKRCOV 0 Initiate Ti e Slot 16 bit C F Counter All Ti e Slot 16 bit C F Counter Sta t to ount Ti e Slot 16 bit C F Counter Keep ounting TKRCOV 1 Tou h key usy flag TKBUSY 0 Gene ate Inte upt equest flag Read C F counter from TKMn16DH TKMn16DL Tou h key s an end Set TKST it 1 0 End Touch Key Manual Scan Mode Flow ...

Page 236: ... Initiate Ti e Slot 16 bit C F Counter All Ti e Slot ounte 16 bit C F counter Sta t to ount Ti e Slot 16 bit C F Counter Keep ounting Yes TKRCOV 1 Gene ate Inte upt equest flag Read C F counter value from Data Me o y Se to Tou h key s an end Set TKST it 1 0 End Load Ref OSC inte nal Capa ito value f o Data Me o y Se to Store C F counter value to Data Me o y Se to All key s an finish Yes No Tou h k...

Page 237: ... time slot counter in all modules will be automatically cleared More details regarding the touch key interrupt is located in the interrupt section of the datasheet Progrsmming Considerations After the relevant registers are setup the touch key detection process is initiated the changing the TKST Bit from low to high This will enable and synchronise all relevant oscillators The TKRCOV flag which is...

Page 238: ... voltage condition is indicated when the LVDO bit is set If the LVDO bit is low this indicates that the VDD voltage is above the preset low voltage value The LVDEN bit is used to control the overall on off function of the low voltage detector Setting the bit high will enable the low voltage detector Clearing the bit to zero will switch off the internal low voltage detector circuits As the low volt...

Page 239: ...VDS should be allowed for the circuitry to stabilise before reading the LVDO bit Note also that as the VDD voltage may rise and fall rather slowly at the voltage nears that of VLVD there may be multiple bit LVDO transitions LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi function interrupts providing an alternative means of low voltage d...

Page 240: ...gram is controlled by a series of registers located in the Special Purpose Data Memory as shown in the accompanying table The number of registers depends upon the device chosen but fall into three categories The first is the INTC0 INTC2 registers which setup the primary interrupts the second is the MFI0 MFI3 registers which setup the Multi function interrupts Finally there is an INTEG register to ...

Page 241: ... CTM0PE MFI1 STMAF STMPF CTM1AF CTM1PF STMAE STMPE CTM1AE CTM1PE MFI2 SIMF PTMAF PTMPF SIME PTMAE PTMPE MFI3 DEF LVF DEE LVE Interrupt Registers List INTEG Register Bit 7 6 5 4 3 2 1 0 Name INT1S1 INT1S0 INT0S1 INT0S0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 INT1S1 INT1S0 Interrupt edge control for INT1 pin 00 Disable 01 Rising edge 10 Falling edge 11 Rising and fall...

Page 242: ...ted read as 0 Bit 6 TKMF Touch key interrupt request flag 0 No request 1 Interrupt request Bit 5 INT1F INT1 interrupt request flag 0 No request 1 Interrupt request Bit 4 INT0F INT0 interrupt request flag 0 No request 1 Interrupt request Bit 3 TKME Touch key interrupt control 0 Disable 1 Enable Bit 2 INT1E INT1 interrupt control 0 Disable 1 Enable Bit 1 INT0E INT0 interrupt control 0 Disable 1 Enab...

Page 243: ...rupt request Bit 6 MF1F Multi function 1 interrupt request flag 0 No request 1 Interrupt request Bit 5 MF0F Multi function 0 interrupt request flag 0 No request 1 Interrupt request Bit 4 URF UART transfer interrupt request flag 0 No request 1 Interrupt request Bit 3 ADE A D Converter interrupt control 0 Disable 1 Enable Bit 2 MF1E Multi function 1 interrupt control 0 Disable 1 Enable Bit 1 MF0E Mu...

Page 244: ...rrupt request Bit 3 MF3E Multi function 3 interrupt control 0 Disable 1 Enable Bit 2 TB1E Time Base 1 interrupt control 0 Disable 1 Enable Bit 1 TB0E Time Base 0 interrupt control 0 Disable 1 Enable Bit 0 MF2E Multi function 2 interrupt control 0 Disable 1 Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Name CTM0AF CTM0PF CTM0AE CTM0PE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5...

Page 245: ...PF STM Comparator P match Interrupt request flag 0 No request 1 Interrupt request Bit 5 CTM1AF CTM1 Comparator A match Interrupt request flag 0 No request 1 Interrupt request Bit 4 CTM1PF CTM1 Comparator P match Interrupt request flag 0 No request 1 Interrupt request Bit 3 STMAE STM Comparator A match Interrupt control 0 Disable 1 Enable Bit 2 STMPE STM Comparator P match Interrupt control 0 Disab...

Page 246: ... flag 0 No request 1 Interrupt request Bit 3 Unimplemented read as 0 Bit 2 SIME SIM Interrupt control 0 Disable 1 Enable Bit 1 PTMAE PTM Comparator A match Interrupt control 0 Disable 1 Enable Bit 0 PTMPE PTM Comparator P match Interrupt control 0 Disable 1 Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Name DEF LVF DEE LVE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 7 DEF Data E...

Page 247: ...utine must be terminated with a RETI which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred The various interrupt enable bits together with their associated request flags are shown in the accompanying diagrams with their order of priority Some interrupt sources have their own ind...

Page 248: ...obal interrupt enable bit EMI and respective external interrupt enable bit INT0E INT1E must first be set Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type As the external interrupt pins are pin shared with I O pins they can only be configured as external interrupt pins if their extern...

Page 249: ...take place when the A D Converter Interrupt request flag ADF is set which occurs when the A D conversion process finishes To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI and A D Interrupt enable bit ADE must first be set When the interrupt is enabled the stack is not full and the A D conversion process has ended a subroutine call to the...

Page 250: ...me periods Its clock source fPSC0 or fPSC1 originates from the internal clock source fSYS fSYS 4 or fSUB and then passes through a divider the division ratio of which is selected by programming the appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL0...

Page 251: ...B02 TB00 Time Base 0 time out period selection 000 28 fPSC0 001 29 fPSC0 010 210 fPSC0 011 211 fPSC0 100 212 fPSC0 101 213 fPSC0 110 214 fPSC0 111 215 fPSC0 TB1C Register Bit 7 6 5 4 3 2 1 0 Name TB1ON TB12 TB11 TB10 R W R W R W R W R W POR 0 0 0 0 Bit 7 TB1ON Time Base 1 Enable Control 0 Disable 1 Enable Bit 6 3 Unimplemented read as 0 Bit 2 0 TB12 TB10 Time Base 1 time out period selection 000 2...

Page 252: ... set When the interrupt is enabled the stack is not full and a low voltage condition occurs a subroutine call to the Multi function Interrupt vector will take place When the Low Voltage Interrupt is serviced the EMI bit will be automatically cleared to disable other interrupts However only the Multi function interrupt request flag will be also automatically cleared As the LVF flag will not be auto...

Page 253: ...quested interrupt can be prevented from being serviced however once an interrupt request flag is set it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program Where a certain interrupt is contained within a Multi function interrupt then when the interrupt service routine is executed as on...

Page 254: ...ouch A D Flash MCU with LCD Driver Application Circuits A D RX VDD VSS BS67F3x0 10µF 0 1µF VDD RS488 Transceiver TX I O RS_DIR Analog Signals KEY1 KEYx XT1 XT2 32768Hz TM PWM Capture TM Buzzer SPI I C Co uni ation Devi e OSC1 OSC Syste C ystal I O Cont ol Devi e COM0 COM3 SEGx ...

Page 255: ... also take one more cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is inv...

Page 256: ... useful set of branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual Bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined ...

Page 257: ...a Memory from ACC with Carry result in Data Memory 1Note Z C AC OV SC CZ DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical ...

Page 258: ...routine 2 None RET A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None ITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None ITABRDL m Increment table pointer ...

Page 259: ...for Addition with result in Data Memory 2Note C Logic Operation LAND A m Logical AND Data Memory to ACC 2 Z LOR A m Logical OR Data Memory to ACC 2 Z LXOR A m Logical XOR Data Memory to ACC 2 Z LANDM A m Logical AND ACC to Data Memory 2Note Z LORM A m Logical OR ACC to Data Memory 2Note Z LXORM A m Logical XOR ACC to Data Memory 2Note Z LCPL m Complement Data Memory 2Note Z LCPLA m Complement Data...

Page 260: ...Memory is zero with result in ACC 2Note None Table Read LTABRD m Read table to TBLH and Data Memory 3Note None LTABRDL m Read table last page to TBLH and Data Memory 3Note None LITABRD m Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL m Increment table pointer TBLP first and Read table last page to TBLH and Data Memory 3Note None Miscellaneous LCLR m C...

Page 261: ...ntents of the Accumulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C SC ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC AND A m Logical AND Data Memo...

Page 262: ...mplement Bits which previously contained a 1 are changed to 0 and vice versa Operation m m Affected flag s Z CPLA m Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented 1 s complement Bits which previously contained a 1 are changed to 0 and vice versa The complemented result is stored in the Accumulator and the contents of the Data M...

Page 263: ...incremented by 1 Operation m m 1 Affected flag s Z INCA m Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1 The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC m 1 Affected flag s Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified ...

Page 264: ... ACC OR m Affected flag s Z RET Return from subroutine Description The Program Counter is restored from the stack Program execution continues at the restored address Operation Program Counter Stack Affected flag s None RET A x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data...

Page 265: ... 1 bit Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 C C m 7 Affected flag s C RR m Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7 Operatio...

Page 266: ... to 1 Operation ACC ACC m C Affected flag s OV Z AC C SC CZ SBCM A m Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Data Memory Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if t...

Page 267: ...of a dummy instruction while the next instruction is fetched it is a two cycle instruction If the result is not 0 the program proceeds with the following instruction Operation ACC m 1 Skip if ACC 0 Affected flag s None SNZ m i Skip if Data Memory is not 0 Description If the specified Data Memory is not 0 the following instruction is skipped As this requires the insertion of a dummy instruction whi...

Page 268: ...he specified Data Memory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next ...

Page 269: ... high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None ITABRDL m Increment table pointer low byte first and read table last page to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high...

Page 270: ...ed The result is stored in the Accumulator Operation ACC ACC m Affected flag s OV Z AC C SC LADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C SC LAND A m Logical AND Data Memory to ACC Description Data in the Accumulator and the specified ...

Page 271: ...remains unchanged If the high nibble is greater than 9 or if the C flag is set then a value of 6 will be added to the high nibble Essentially the decimal conversion is performed by adding 00H 06H 60H or 66H depending on the Accumulator and flag conditions Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precisio...

Page 272: ...pecified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 Operation m i 1 m i i 0 6 m 0 m 7 Affected flag s None LRLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operati...

Page 273: ...on Data in the specified Data Memory and the carry flag are rotated right by 1 bit Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i m i 1 i 0 6 ACC 7 C C m 0 Affected flag s C LSBC A m Subtract Data Memory from ACC with Carry Description The contents of...

Page 274: ...ory Description Bit i of the specified Data Memory is set to 1 Operation m i 1 Affected flag s None LSIZ m Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it is a two cycle instruction...

Page 275: ... the C flag will be set to 1 Operation m ACC m Affected flag s OV Z AC C SC CZ LSWAP m Swap nibbles of Data Memory Description The low order and high order nibbles of the specified Data Memory are interchanged Operation m 3 m 0 m 7 m 4 Affected flag s None LSWAPA m Swap nibbles of Data Memory with result in ACC Description The low order and high order nibbles of the specified Data Memory are inter...

Page 276: ... code high byte Affected flag s None LITABRD m Increment table pointer low byte first and read table to TBLH and Data Memory Description Increment table pointer low byte TBLP first and then the program code addressed by the table pointer TBHP and TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s ...

Page 277: ...ay be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Further Package Information include Outline Dimensions Product Tape and Reel Specifications Packing Mete...

Page 278: ...x A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 020 BSC D2 0 170 0 205 E2 0 079 F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 00 BSC B 7 00 BSC C 9 00 BSC D 7 00 BSC E 0 50 BSC D2 4 31 5 21 E2 2 00 F 0 17 0 22 0 27 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 279: ...ions in inch Min Nom Max A 0 354 BSC B 0 276 BSC C 0 354 BSC D 0 276 BSC E 0 016 BSC F 0 005 0 007 0 009 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 9 00 BSC B 7 00 BSC C 9 00 BSC D 7 00 BSC E 0 40 BSC F 0 13 0 18 0 23 G 1 35 1 40 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 280: ...imensions in inch Min Nom Max A 0 472 BSC B 0 394 BSC C 0 472 BSC D 0 394 BSC E 0 0157 BSC F 0 007 0 009 0 011 G 0 053 0 055 0 057 H 0 063 I 0 002 0 006 J 0 018 0 024 0 030 K 0 004 0 008 α 0 7 Symbol Dimensions in mm Min Nom Max A 12 BSC B 10 BSC C 12 BSC D 10 BSC E 0 4 BSC F 0 13 0 18 0 23 G 1 35 1 4 1 45 H 1 60 I 0 05 0 15 J 0 45 0 60 0 75 K 0 09 0 20 α 0 7 ...

Page 281: ...tioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or sy...

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