HMS Ixxat iPC-I 320, Hardware Manual

Page: 18 / 28

Architecture
18
iPC-I 320 Manual, Version 2.8
4 Architecture
4.1 PC Side Memory Assignment
Communication with the PC is made via a 7 kbyte memory zone in which the 4
kbyte DPRAM, eight semaphore registers and 2 flags (Reset and µC-interrupt)
are placed.
INT
µ
C (INT2)
Semaphores
Reset iPC-I 320
DPRAM
(4 kbyte)
Offset
1BFFh
1800h
1400h
1000h
0000h base address
Fig. 4-1: PC side memory assignment
4.1.1 DPRAM
Generally the DPRAM can be accessed from both sides simultaneously.
However, this only applies if it is not the same address. In this case
differentiation is made between the types of access. Reading from both sides is
unproblematic here. However, if writing occurs from one side and reading from
the other, the reading side receives either the old data or the data just written. If
writing occurs simultaneously from both sides onto the same memory cell, an
access conflict occurs. Using so-called semaphores can prevent this collision.
4.1.2 Semaphores
Semaphores, also referred to in this context as semaphore registers, are special
memory cells in the DPRAM. They are in a zone which is isolated from the actual
DPRAM.
The DPRAM used has eight of such semaphore registers. For their selection,
only the three lower value address lines are important, i.e. the eight registers
are reflected just as frequently in the range from 1000h to 13FFh (PC side) or
from F000h to F3FFh (µC side).
For more information on DPRAM and its semaphore registers, please see the
data sheet of the IDT 71342 (addresses in Appendix C).